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Diffstat (limited to 'arch/mips/sni/rm200.c')
-rw-r--r--arch/mips/sni/rm200.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 5310aa75afa4..5e687819cbc2 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -359,7 +359,8 @@ void sni_rm200_init_8259A(void)
359 * IRQ2 is cascade interrupt to second interrupt controller 359 * IRQ2 is cascade interrupt to second interrupt controller
360 */ 360 */
361static struct irqaction sni_rm200_irq2 = { 361static struct irqaction sni_rm200_irq2 = {
362 no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL 362 .handler = no_action,
363 .name = "cascade",
363}; 364};
364 365
365static struct resource sni_rm200_pic1_resource = { 366static struct resource sni_rm200_pic1_resource = {
@@ -487,7 +488,7 @@ void __init sni_rm200_irq_init(void)
487 mips_cpu_irq_init(); 488 mips_cpu_irq_init();
488 /* Actually we've got more interrupts to handle ... */ 489 /* Actually we've got more interrupts to handle ... */
489 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) 490 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
490 set_irq_chip(i, &rm200_irq_type); 491 set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
491 sni_hwint = sni_rm200_hwint; 492 sni_hwint = sni_rm200_hwint;
492 change_c0_status(ST0_IM, IE_IRQ0); 493 change_c0_status(ST0_IM, IE_IRQ0);
493 setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); 494 setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);