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-rw-r--r--arch/mips/sni/irq.c188
1 files changed, 44 insertions, 144 deletions
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 039e8e540508..ad5fc471a004 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -5,6 +5,7 @@
5 * 5 *
6 * Copyright (C) 1992 Linus Torvalds 6 * Copyright (C) 1992 Linus Torvalds
7 * Copyright (C) 1994 - 2000 Ralf Baechle 7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 2006 Thomas Bogendoerfer
8 */ 9 */
9#include <linux/delay.h> 10#include <linux/delay.h>
10#include <linux/init.h> 11#include <linux/init.h>
@@ -15,152 +16,34 @@
15#include <asm/i8259.h> 16#include <asm/i8259.h>
16#include <asm/io.h> 17#include <asm/io.h>
17#include <asm/sni.h> 18#include <asm/sni.h>
19#include <asm/irq.h>
20#include <asm/irq_cpu.h>
18 21
19static void enable_pciasic_irq(unsigned int irq) 22void (*sni_hwint)(void);
20{
21 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
22
23 *(volatile u8 *) PCIMT_IRQSEL |= mask;
24}
25
26void disable_pciasic_irq(unsigned int irq)
27{
28 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
29
30 *(volatile u8 *) PCIMT_IRQSEL &= mask;
31}
32 23
33static void end_pciasic_irq(unsigned int irq) 24asmlinkage void plat_irq_dispatch(void)
34{
35 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
36 enable_pciasic_irq(irq);
37}
38
39static struct irq_chip pciasic_irq_type = {
40 .name = "ASIC-PCI",
41 .ack = disable_pciasic_irq,
42 .mask = disable_pciasic_irq,
43 .mask_ack = disable_pciasic_irq,
44 .unmask = enable_pciasic_irq,
45 .end = end_pciasic_irq,
46};
47
48/*
49 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
50 * button interrupts. Later ...
51 */
52static void pciasic_hwint0(void)
53{
54 panic("Received int0 but no handler yet ...");
55}
56
57/* This interrupt was used for the com1 console on the first prototypes. */
58static void pciasic_hwint2(void)
59{
60 /* I think this shouldn't happen on production machines. */
61 panic("hwint2 and no handler yet");
62}
63
64/* hwint5 is the r4k count / compare interrupt */
65static void pciasic_hwint5(void)
66{
67 panic("hwint5 and no handler yet");
68}
69
70static unsigned int ls1bit8(unsigned int x)
71{
72 int b = 7, s;
73
74 s = 4; if ((x & 0x0f) == 0) s = 0; b -= s; x <<= s;
75 s = 2; if ((x & 0x30) == 0) s = 0; b -= s; x <<= s;
76 s = 1; if ((x & 0x40) == 0) s = 0; b -= s;
77
78 return b;
79}
80
81/*
82 * hwint 1 deals with EISA and SCSI interrupts,
83 *
84 * The EISA_INT bit in CSITPEND is high active, all others are low active.
85 */
86static void pciasic_hwint1(void)
87{ 25{
88 u8 pend = *(volatile char *)PCIMT_CSITPEND; 26 sni_hwint();
89 unsigned long flags;
90
91 if (pend & IT_EISA) {
92 int irq;
93 /*
94 * Note: ASIC PCI's builtin interrupt achknowledge feature is
95 * broken. Using it may result in loss of some or all i8259
96 * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
97 */
98 irq = i8259_irq();
99 if (unlikely(irq < 0))
100 return;
101
102 do_IRQ(irq);
103 }
104
105 if (!(pend & IT_SCSI)) {
106 flags = read_c0_status();
107 clear_c0_status(ST0_IM);
108 do_IRQ(PCIMT_IRQ_SCSI);
109 write_c0_status(flags);
110 }
111} 27}
112 28
113/* 29/* ISA irq handler */
114 * hwint 3 should deal with the PCI A - D interrupts, 30static irqreturn_t sni_isa_irq_handler(int dummy, void *p)
115 */
116static void pciasic_hwint3(void)
117{ 31{
118 u8 pend = *(volatile char *)PCIMT_CSITPEND;
119 int irq; 32 int irq;
120 33
121 pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD); 34 irq = i8259_irq();
122 clear_c0_status(IE_IRQ3); 35 if (unlikely(irq < 0))
123 irq = PCIMT_IRQ_INT2 + ls1bit8(pend); 36 return IRQ_NONE;
124 do_IRQ(irq);
125 set_c0_status(IE_IRQ3);
126}
127 37
128/* 38 do_IRQ(irq);
129 * hwint 4 is used for only the onboard PCnet 32. 39 return IRQ_HANDLED;
130 */
131static void pciasic_hwint4(void)
132{
133 clear_c0_status(IE_IRQ4);
134 do_IRQ(PCIMT_IRQ_ETHERNET);
135 set_c0_status(IE_IRQ4);
136}
137
138asmlinkage void plat_irq_dispatch(void)
139{
140 unsigned int pending = read_c0_status() & read_c0_cause();
141 static unsigned char led_cache;
142
143 *(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
144
145 if (pending & 0x0800)
146 pciasic_hwint1();
147 else if (pending & 0x4000)
148 pciasic_hwint4();
149 else if (pending & 0x2000)
150 pciasic_hwint3();
151 else if (pending & 0x1000)
152 pciasic_hwint2();
153 else if (pending & 0x8000)
154 pciasic_hwint5();
155 else if (pending & 0x0400)
156 pciasic_hwint0();
157} 40}
158 41
159void __init init_pciasic(void) 42struct irqaction sni_isa_irq = {
160{ 43 .handler = sni_isa_irq_handler,
161 * (volatile u8 *) PCIMT_IRQSEL = 44 .name = "ISA",
162 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD; 45 .flags = SA_SHIRQ
163} 46};
164 47
165/* 48/*
166 * On systems with i8259-style interrupt controllers we assume for 49 * On systems with i8259-style interrupt controllers we assume for
@@ -169,14 +52,31 @@ void __init init_pciasic(void)
169 */ 52 */
170void __init arch_init_irq(void) 53void __init arch_init_irq(void)
171{ 54{
172 int i;
173
174 init_i8259_irqs(); /* Integrated i8259 */ 55 init_i8259_irqs(); /* Integrated i8259 */
175 init_pciasic(); 56 switch (sni_brd_type) {
176 57 case SNI_BRD_10:
177 /* Actually we've got more interrupts to handle ... */ 58 case SNI_BRD_10NEW:
178 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) 59 case SNI_BRD_TOWER_OASIC:
179 set_irq_chip(i, &pciasic_irq_type); 60 case SNI_BRD_MINITOWER:
180 61 sni_a20r_irq_init();
181 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); 62 break;
63
64 case SNI_BRD_PCI_TOWER:
65 sni_pcit_irq_init();
66 break;
67
68 case SNI_BRD_PCI_TOWER_CPLUS:
69 sni_pcit_cplus_irq_init();
70 break;
71
72 case SNI_BRD_RM200:
73 sni_rm200_irq_init();
74 break;
75
76 case SNI_BRD_PCI_MTOWER:
77 case SNI_BRD_PCI_DESKTOP:
78 case SNI_BRD_PCI_MTOWER_CPLUS:
79 sni_pcimt_irq_init();
80 break;
81 }
182} 82}
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