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-rw-r--r--arch/mips/sibyte/Kconfig12
-rw-r--r--arch/mips/sibyte/sb1250/bcm1250_tbprof.c377
-rw-r--r--arch/mips/sibyte/sb1250/setup.c2
3 files changed, 283 insertions, 108 deletions
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index 10cc40304347..bdf24a7b5494 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -8,12 +8,14 @@ config SIBYTE_SB1250
8config SIBYTE_BCM1120 8config SIBYTE_BCM1120
9 bool 9 bool
10 select SIBYTE_BCM112X 10 select SIBYTE_BCM112X
11 select SIBYTE_HAS_ZBUS_PROFILING
11 select SIBYTE_SB1xxx_SOC 12 select SIBYTE_SB1xxx_SOC
12 13
13config SIBYTE_BCM1125 14config SIBYTE_BCM1125
14 bool 15 bool
15 select HW_HAS_PCI 16 select HW_HAS_PCI
16 select SIBYTE_BCM112X 17 select SIBYTE_BCM112X
18 select SIBYTE_HAS_ZBUS_PROFILING
17 select SIBYTE_SB1xxx_SOC 19 select SIBYTE_SB1xxx_SOC
18 20
19config SIBYTE_BCM1125H 21config SIBYTE_BCM1125H
@@ -21,11 +23,13 @@ config SIBYTE_BCM1125H
21 select HW_HAS_PCI 23 select HW_HAS_PCI
22 select SIBYTE_BCM112X 24 select SIBYTE_BCM112X
23 select SIBYTE_ENABLE_LDT_IF_PCI 25 select SIBYTE_ENABLE_LDT_IF_PCI
26 select SIBYTE_HAS_ZBUS_PROFILING
24 select SIBYTE_SB1xxx_SOC 27 select SIBYTE_SB1xxx_SOC
25 28
26config SIBYTE_BCM112X 29config SIBYTE_BCM112X
27 bool 30 bool
28 select SIBYTE_SB1xxx_SOC 31 select SIBYTE_SB1xxx_SOC
32 select SIBYTE_HAS_ZBUS_PROFILING
29 33
30config SIBYTE_BCM1x80 34config SIBYTE_BCM1x80
31 bool 35 bool
@@ -37,6 +41,7 @@ config SIBYTE_BCM1x55
37 bool 41 bool
38 select HW_HAS_PCI 42 select HW_HAS_PCI
39 select SIBYTE_SB1xxx_SOC 43 select SIBYTE_SB1xxx_SOC
44 select SIBYTE_HAS_ZBUS_PROFILING
40 select SYS_SUPPORTS_SMP 45 select SYS_SUPPORTS_SMP
41 46
42config SIBYTE_SB1xxx_SOC 47config SIBYTE_SB1xxx_SOC
@@ -164,5 +169,8 @@ config SIBYTE_SB1250_PROF
164 depends on SIBYTE_SB1xxx_SOC 169 depends on SIBYTE_SB1xxx_SOC
165 170
166config SIBYTE_TBPROF 171config SIBYTE_TBPROF
167 bool "Support for ZBbus profiling" 172 tristate "Support for ZBbus profiling"
168 depends on SIBYTE_SB1xxx_SOC 173 depends on SIBYTE_HAS_ZBUS_PROFILING
174
175config SIBYTE_HAS_ZBUS_PROFILING
176 bool
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
index 212547c57310..ea0ca131a3cf 100644
--- a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
+++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or 2 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 3 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2 4 * as published by the Free Software Foundation; either version 2
@@ -14,10 +12,16 @@
14 * You should have received a copy of the GNU General Public License 12 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software 13 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
17 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
18 * Copyright (C) 2007 MIPS Technologies, Inc.
19 * written by Ralf Baechle <ralf@linux-mips.org>
17 */ 20 */
18 21
19#define SBPROF_TB_DEBUG 0 22#undef DEBUG
20 23
24#include <linux/device.h>
21#include <linux/module.h> 25#include <linux/module.h>
22#include <linux/kernel.h> 26#include <linux/kernel.h>
23#include <linux/types.h> 27#include <linux/types.h>
@@ -27,24 +31,98 @@
27#include <linux/vmalloc.h> 31#include <linux/vmalloc.h>
28#include <linux/fs.h> 32#include <linux/fs.h>
29#include <linux/errno.h> 33#include <linux/errno.h>
30#include <linux/reboot.h> 34#include <linux/types.h>
31#include <linux/smp_lock.h>
32#include <linux/wait.h> 35#include <linux/wait.h>
33#include <asm/uaccess.h> 36
34#include <asm/io.h> 37#include <asm/io.h>
35#include <asm/sibyte/sb1250.h> 38#include <asm/sibyte/sb1250.h>
36#include <asm/sibyte/sb1250_regs.h> 39#include <asm/sibyte/sb1250_regs.h>
37#include <asm/sibyte/sb1250_scd.h> 40#include <asm/sibyte/sb1250_scd.h>
38#include <asm/sibyte/sb1250_int.h> 41#include <asm/sibyte/sb1250_int.h>
39#include <asm/sibyte/trace_prof.h> 42#include <asm/system.h>
43#include <asm/uaccess.h>
40 44
41#define DEVNAME "bcm1250_tbprof" 45#define SBPROF_TB_MAJOR 240
46
47typedef u64 tb_sample_t[6*256];
48
49enum open_status {
50 SB_CLOSED,
51 SB_OPENING,
52 SB_OPEN
53};
54
55struct sbprof_tb {
56 wait_queue_head_t tb_sync;
57 wait_queue_head_t tb_read;
58 struct mutex lock;
59 enum open_status open;
60 tb_sample_t *sbprof_tbbuf;
61 int next_tb_sample;
62
63 volatile int tb_enable;
64 volatile int tb_armed;
65
66};
42 67
43static struct sbprof_tb sbp; 68static struct sbprof_tb sbp;
44 69
70#define MAX_SAMPLE_BYTES (24*1024*1024)
71#define MAX_TBSAMPLE_BYTES (12*1024*1024)
72
73#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
74#define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
75#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
76
77/* ioctls */
78#define SBPROF_ZBSTART _IOW('s', 0, int)
79#define SBPROF_ZBSTOP _IOW('s', 1, int)
80#define SBPROF_ZBWAITFULL _IOW('s', 2, int)
81
82/*
83 * Routines for using 40-bit SCD cycle counter
84 *
85 * Client responsible for either handling interrupts or making sure
86 * the cycles counter never saturates, e.g., by doing
87 * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
88 */
89
90/*
91 * Configures SCD counter 0 to count ZCLKs starting from val;
92 * Configures SCD counters1,2,3 to count nothing.
93 * Must not be called while gathering ZBbus profiles.
94 */
95
96#define zclk_timer_init(val) \
97 __asm__ __volatile__ (".set push;" \
98 ".set mips64;" \
99 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
100 "sd %0, 0x10($8);" /* write val to counter0 */ \
101 "sd %1, 0($8);" /* config counter0 for zclks*/ \
102 ".set pop" \
103 : /* no outputs */ \
104 /* enable, counter0 */ \
105 : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
106 : /* modifies */ "$8" )
107
108
109/* Reads SCD counter 0 and puts result in value
110 unsigned long long val; */
111#define zclk_get(val) \
112 __asm__ __volatile__ (".set push;" \
113 ".set mips64;" \
114 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
115 "ld %0, 0x10($8);" /* write val to counter0 */ \
116 ".set pop" \
117 : /* outputs */ "=r"(val) \
118 : /* inputs */ \
119 : /* modifies */ "$8" )
120
121#define DEVNAME "bcm1250_tbprof"
122
45#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES) 123#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
46 124
47/************************************************************************ 125/*
48 * Support for ZBbus sampling using the trace buffer 126 * Support for ZBbus sampling using the trace buffer
49 * 127 *
50 * We use the SCD performance counter interrupt, caused by a Zclk counter 128 * We use the SCD performance counter interrupt, caused by a Zclk counter
@@ -54,30 +132,36 @@ static struct sbprof_tb sbp;
54 * overflow. 132 * overflow.
55 * 133 *
56 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0. 134 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
57 * 135 */
58 ************************************************************************/
59 136
60static u_int64_t tb_period; 137static u64 tb_period;
61 138
62static void arm_tb(void) 139static void arm_tb(void)
63{ 140{
64 u_int64_t scdperfcnt; 141 u64 scdperfcnt;
65 u_int64_t next = (1ULL << 40) - tb_period; 142 u64 next = (1ULL << 40) - tb_period;
66 u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; 143 u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
67 /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to 144
68 trigger start of trace. XXX vary sampling period */ 145 /*
146 * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to trigger
147 *start of trace. XXX vary sampling period
148 */
69 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); 149 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
70 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 150 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
71 /* Unfortunately, in Pass 2 we must clear all counters to knock down 151
72 a previous interrupt request. This means that bus profiling 152 /*
73 requires ALL of the SCD perf counters. */ 153 * Unfortunately, in Pass 2 we must clear all counters to knock down a
154 * previous interrupt request. This means that bus profiling requires
155 * ALL of the SCD perf counters.
156 */
74 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | 157 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
75 // keep counters 0,2,3 as is 158 /* keep counters 0,2,3 as is */
76 M_SPC_CFG_ENABLE | // enable counting 159 M_SPC_CFG_ENABLE | /* enable counting */
77 M_SPC_CFG_CLEAR | // clear all counters 160 M_SPC_CFG_CLEAR | /* clear all counters */
78 V_SPC_CFG_SRC1(1), // counter 1 counts cycles 161 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
79 IOADDR(A_SCD_PERF_CNT_CFG)); 162 IOADDR(A_SCD_PERF_CNT_CFG));
80 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); 163 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
164
81 /* Reset the trace buffer */ 165 /* Reset the trace buffer */
82 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 166 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
83#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) 167#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
@@ -91,43 +175,45 @@ static void arm_tb(void)
91static irqreturn_t sbprof_tb_intr(int irq, void *dev_id) 175static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
92{ 176{
93 int i; 177 int i;
94 DBG(printk(DEVNAME ": tb_intr\n")); 178
179 pr_debug(DEVNAME ": tb_intr\n");
180
95 if (sbp.next_tb_sample < MAX_TB_SAMPLES) { 181 if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
96 /* XXX should use XKPHYS to make writes bypass L2 */ 182 /* XXX should use XKPHYS to make writes bypass L2 */
97 u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; 183 u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
98 /* Read out trace */ 184 /* Read out trace */
99 __raw_writeq(M_SCD_TRACE_CFG_START_READ, 185 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
100 IOADDR(A_SCD_TRACE_CFG)); 186 IOADDR(A_SCD_TRACE_CFG));
101 __asm__ __volatile__ ("sync" : : : "memory"); 187 __asm__ __volatile__ ("sync" : : : "memory");
102 /* Loop runs backwards because bundles are read out in reverse order */ 188 /* Loop runs backwards because bundles are read out in reverse order */
103 for (i = 256 * 6; i > 0; i -= 6) { 189 for (i = 256 * 6; i > 0; i -= 6) {
104 // Subscripts decrease to put bundle in the order 190 /* Subscripts decrease to put bundle in the order */
105 // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi 191 /* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
106 p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 192 p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
107 // read t2 hi 193 /* read t2 hi */
108 p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 194 p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
109 // read t2 lo 195 /* read t2 lo */
110 p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 196 p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
111 // read t1 hi 197 /* read t1 hi */
112 p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 198 p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
113 // read t1 lo 199 /* read t1 lo */
114 p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 200 p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
115 // read t0 hi 201 /* read t0 hi */
116 p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 202 p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
117 // read t0 lo 203 /* read t0 lo */
118 } 204 }
119 if (!sbp.tb_enable) { 205 if (!sbp.tb_enable) {
120 DBG(printk(DEVNAME ": tb_intr shutdown\n")); 206 pr_debug(DEVNAME ": tb_intr shutdown\n");
121 __raw_writeq(M_SCD_TRACE_CFG_RESET, 207 __raw_writeq(M_SCD_TRACE_CFG_RESET,
122 IOADDR(A_SCD_TRACE_CFG)); 208 IOADDR(A_SCD_TRACE_CFG));
123 sbp.tb_armed = 0; 209 sbp.tb_armed = 0;
124 wake_up(&sbp.tb_sync); 210 wake_up(&sbp.tb_sync);
125 } else { 211 } else {
126 arm_tb(); // knock down current interrupt and get another one later 212 arm_tb(); /* knock down current interrupt and get another one later */
127 } 213 }
128 } else { 214 } else {
129 /* No more trace buffer samples */ 215 /* No more trace buffer samples */
130 DBG(printk(DEVNAME ": tb_intr full\n")); 216 pr_debug(DEVNAME ": tb_intr full\n");
131 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 217 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
132 sbp.tb_armed = 0; 218 sbp.tb_armed = 0;
133 if (!sbp.tb_enable) { 219 if (!sbp.tb_enable) {
@@ -135,6 +221,7 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
135 } 221 }
136 wake_up(&sbp.tb_read); 222 wake_up(&sbp.tb_read);
137 } 223 }
224
138 return IRQ_HANDLED; 225 return IRQ_HANDLED;
139} 226}
140 227
@@ -144,23 +231,30 @@ static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
144 return IRQ_NONE; 231 return IRQ_NONE;
145} 232}
146 233
147int sbprof_zbprof_start(struct file *filp) 234/*
235 * Requires: Already called zclk_timer_init with a value that won't
236 * saturate 40 bits. No subsequent use of SCD performance counters
237 * or trace buffer.
238 */
239
240static int sbprof_zbprof_start(struct file *filp)
148{ 241{
149 u_int64_t scdperfcnt; 242 u64 scdperfcnt;
243 int err;
150 244
151 if (sbp.tb_enable) 245 if (xchg(&sbp.tb_enable, 1))
152 return -EBUSY; 246 return -EBUSY;
153 247
154 DBG(printk(DEVNAME ": starting\n")); 248 pr_debug(DEVNAME ": starting\n");
155 249
156 sbp.tb_enable = 1;
157 sbp.next_tb_sample = 0; 250 sbp.next_tb_sample = 0;
158 filp->f_pos = 0; 251 filp->f_pos = 0;
159 252
160 if (request_irq 253 err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
161 (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) { 254 DEVNAME " trace freeze", &sbp);
255 if (err)
162 return -EBUSY; 256 return -EBUSY;
163 } 257
164 /* Make sure there isn't a perf-cnt interrupt waiting */ 258 /* Make sure there isn't a perf-cnt interrupt waiting */
165 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 259 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
166 /* Disable and clear counters, override SRC_1 */ 260 /* Disable and clear counters, override SRC_1 */
@@ -168,18 +262,21 @@ int sbprof_zbprof_start(struct file *filp)
168 M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1), 262 M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
169 IOADDR(A_SCD_PERF_CNT_CFG)); 263 IOADDR(A_SCD_PERF_CNT_CFG));
170 264
171 /* We grab this interrupt to prevent others from trying to use 265 /*
172 it, even though we don't want to service the interrupts 266 * We grab this interrupt to prevent others from trying to use it, even
173 (they only feed into the trace-on-interrupt mechanism) */ 267 * though we don't want to service the interrupts (they only feed into
174 if (request_irq 268 * the trace-on-interrupt mechanism)
175 (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) { 269 */
176 free_irq(K_INT_TRACE_FREEZE, &sbp); 270 err = request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0,
177 return -EBUSY; 271 DEVNAME " scd perfcnt", &sbp);
178 } 272 if (err)
179 273 goto out_free_irq;
180 /* I need the core to mask these, but the interrupt mapper to 274
181 pass them through. I am exploiting my knowledge that 275 /*
182 cp0_status masks out IP[5]. krw */ 276 * I need the core to mask these, but the interrupt mapper to pass them
277 * through. I am exploiting my knowledge that cp0_status masks out
278 * IP[5]. krw
279 */
183 __raw_writeq(K_INT_MAP_I3, 280 __raw_writeq(K_INT_MAP_I3,
184 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 281 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
185 (K_INT_PERF_CNT << 3))); 282 (K_INT_PERF_CNT << 3)));
@@ -201,7 +298,7 @@ int sbprof_zbprof_start(struct file *filp)
201 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); 298 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
202 299
203 /* Initialize Trace Event 0-7 */ 300 /* Initialize Trace Event 0-7 */
204 // when interrupt 301 /* when interrupt */
205 __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); 302 __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
206 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); 303 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
207 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); 304 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
@@ -212,10 +309,10 @@ int sbprof_zbprof_start(struct file *filp)
212 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); 309 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
213 310
214 /* Initialize Trace Sequence 0-7 */ 311 /* Initialize Trace Sequence 0-7 */
215 // Start on event 0 (interrupt) 312 /* Start on event 0 (interrupt) */
216 __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, 313 __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
217 IOADDR(A_SCD_TRACE_SEQUENCE_0)); 314 IOADDR(A_SCD_TRACE_SEQUENCE_0));
218 // dsamp when d used | asamp when a used 315 /* dsamp when d used | asamp when a used */
219 __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | 316 __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
220 K_SCD_TRSEQ_TRIGGER_ALL, 317 K_SCD_TRSEQ_TRIGGER_ALL,
221 IOADDR(A_SCD_TRACE_SEQUENCE_1)); 318 IOADDR(A_SCD_TRACE_SEQUENCE_1));
@@ -232,33 +329,41 @@ int sbprof_zbprof_start(struct file *filp)
232 329
233 arm_tb(); 330 arm_tb();
234 331
235 DBG(printk(DEVNAME ": done starting\n")); 332 pr_debug(DEVNAME ": done starting\n");
236 333
237 return 0; 334 return 0;
335
336out_free_irq:
337 free_irq(K_INT_TRACE_FREEZE, &sbp);
338
339 return err;
238} 340}
239 341
240int sbprof_zbprof_stop(void) 342static int sbprof_zbprof_stop(void)
241{ 343{
242 DEFINE_WAIT(wait); 344 int err;
243 DBG(printk(DEVNAME ": stopping\n")); 345
346 pr_debug(DEVNAME ": stopping\n");
244 347
245 if (sbp.tb_enable) { 348 if (sbp.tb_enable) {
349 /*
350 * XXXKW there is a window here where the intr handler may run,
351 * see the disable, and do the wake_up before this sleep
352 * happens.
353 */
354 pr_debug(DEVNAME ": wait for disarm\n");
355 err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
356 pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
357
358 if (err)
359 return err;
360
246 sbp.tb_enable = 0; 361 sbp.tb_enable = 0;
247 /* XXXKW there is a window here where the intr handler
248 may run, see the disable, and do the wake_up before
249 this sleep happens. */
250 if (sbp.tb_armed) {
251 DBG(printk(DEVNAME ": wait for disarm\n"));
252 prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE);
253 schedule();
254 finish_wait(&sbp.tb_sync, &wait);
255 DBG(printk(DEVNAME ": disarm complete\n"));
256 }
257 free_irq(K_INT_TRACE_FREEZE, &sbp); 362 free_irq(K_INT_TRACE_FREEZE, &sbp);
258 free_irq(K_INT_PERF_CNT, &sbp); 363 free_irq(K_INT_PERF_CNT, &sbp);
259 } 364 }
260 365
261 DBG(printk(DEVNAME ": done stopping\n")); 366 pr_debug(DEVNAME ": done stopping\n");
262 367
263 return 0; 368 return 0;
264} 369}
@@ -268,42 +373,45 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp)
268 int minor; 373 int minor;
269 374
270 minor = iminor(inode); 375 minor = iminor(inode);
271 if (minor != 0) { 376 if (minor != 0)
272 return -ENODEV; 377 return -ENODEV;
273 } 378
274 if (sbp.open) { 379 if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
275 return -EBUSY; 380 return -EBUSY;
276 }
277 381
278 memset(&sbp, 0, sizeof(struct sbprof_tb)); 382 memset(&sbp, 0, sizeof(struct sbprof_tb));
383
279 sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES); 384 sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
280 if (!sbp.sbprof_tbbuf) { 385 if (!sbp.sbprof_tbbuf)
281 return -ENOMEM; 386 return -ENOMEM;
282 } 387
283 memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES); 388 memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
284 init_waitqueue_head(&sbp.tb_sync); 389 init_waitqueue_head(&sbp.tb_sync);
285 init_waitqueue_head(&sbp.tb_read); 390 init_waitqueue_head(&sbp.tb_read);
286 sbp.open = 1; 391 mutex_init(&sbp.lock);
392
393 sbp.open = SB_OPEN;
287 394
288 return 0; 395 return 0;
289} 396}
290 397
291static int sbprof_tb_release(struct inode *inode, struct file *filp) 398static int sbprof_tb_release(struct inode *inode, struct file *filp)
292{ 399{
293 int minor; 400 int minor = iminor(inode);
294 401
295 minor = iminor(inode); 402 if (minor != 0 || !sbp.open)
296 if (minor != 0 || !sbp.open) {
297 return -ENODEV; 403 return -ENODEV;
298 }
299 404
300 if (sbp.tb_armed || sbp.tb_enable) { 405 mutex_lock(&sbp.lock);
406
407 if (sbp.tb_armed || sbp.tb_enable)
301 sbprof_zbprof_stop(); 408 sbprof_zbprof_stop();
302 }
303 409
304 vfree(sbp.sbprof_tbbuf); 410 vfree(sbp.sbprof_tbbuf);
305 sbp.open = 0; 411 sbp.open = 0;
306 412
413 mutex_unlock(&sbp.lock);
414
307 return 0; 415 return 0;
308} 416}
309 417
@@ -311,21 +419,35 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
311 size_t size, loff_t *offp) 419 size_t size, loff_t *offp)
312{ 420{
313 int cur_sample, sample_off, cur_count, sample_left; 421 int cur_sample, sample_off, cur_count, sample_left;
314 char *src;
315 int count = 0;
316 char *dest = buf;
317 long cur_off = *offp; 422 long cur_off = *offp;
423 char *dest = buf;
424 int count = 0;
425 char *src;
426
427 if (!access_ok(VERIFY_WRITE, buf, size))
428 return -EFAULT;
429
430 mutex_lock(&sbp.lock);
318 431
319 count = 0; 432 count = 0;
320 cur_sample = cur_off / TB_SAMPLE_SIZE; 433 cur_sample = cur_off / TB_SAMPLE_SIZE;
321 sample_off = cur_off % TB_SAMPLE_SIZE; 434 sample_off = cur_off % TB_SAMPLE_SIZE;
322 sample_left = TB_SAMPLE_SIZE - sample_off; 435 sample_left = TB_SAMPLE_SIZE - sample_off;
436
323 while (size && (cur_sample < sbp.next_tb_sample)) { 437 while (size && (cur_sample < sbp.next_tb_sample)) {
438 int err;
439
324 cur_count = size < sample_left ? size : sample_left; 440 cur_count = size < sample_left ? size : sample_left;
325 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off); 441 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
326 copy_to_user(dest, src, cur_count); 442 err = __copy_to_user(dest, src, cur_count);
327 DBG(printk(DEVNAME ": read from sample %d, %d bytes\n", 443 if (err) {
328 cur_sample, cur_count)); 444 *offp = cur_off + cur_count - err;
445 mutex_unlock(&sbp.lock);
446 return err;
447 }
448
449 pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
450 cur_sample, cur_count);
329 size -= cur_count; 451 size -= cur_count;
330 sample_left -= cur_count; 452 sample_left -= cur_count;
331 if (!sample_left) { 453 if (!sample_left) {
@@ -339,37 +461,43 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
339 dest += cur_count; 461 dest += cur_count;
340 count += cur_count; 462 count += cur_count;
341 } 463 }
464
342 *offp = cur_off; 465 *offp = cur_off;
466 mutex_unlock(&sbp.lock);
343 467
344 return count; 468 return count;
345} 469}
346 470
347static long sbprof_tb_ioctl(struct file *filp, 471static long sbprof_tb_ioctl(struct file *filp, unsigned int command,
348 unsigned int command, 472 unsigned long arg)
349 unsigned long arg)
350{ 473{
351 int error = 0; 474 int error = 0;
352 475
353 lock_kernel();
354 switch (command) { 476 switch (command) {
355 case SBPROF_ZBSTART: 477 case SBPROF_ZBSTART:
478 mutex_lock(&sbp.lock);
356 error = sbprof_zbprof_start(filp); 479 error = sbprof_zbprof_start(filp);
480 mutex_unlock(&sbp.lock);
357 break; 481 break;
482
358 case SBPROF_ZBSTOP: 483 case SBPROF_ZBSTOP:
484 mutex_lock(&sbp.lock);
359 error = sbprof_zbprof_stop(); 485 error = sbprof_zbprof_stop();
486 mutex_unlock(&sbp.lock);
360 break; 487 break;
488
361 case SBPROF_ZBWAITFULL: 489 case SBPROF_ZBWAITFULL:
362 DEFINE_WAIT(wait); 490 error = wait_event_interruptible(sbp.tb_read, TB_FULL);
363 prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE); 491 if (error)
364 schedule(); 492 break;
365 finish_wait(&sbp.tb_read, &wait); 493
366 /* XXXKW check if interrupted? */ 494 error = put_user(TB_FULL, (int *) arg);
367 return put_user(TB_FULL, (int *) arg); 495 break;
496
368 default: 497 default:
369 error = -EINVAL; 498 error = -EINVAL;
370 break; 499 break;
371 } 500 }
372 unlock_kernel();
373 501
374 return error; 502 return error;
375} 503}
@@ -384,23 +512,60 @@ static const struct file_operations sbprof_tb_fops = {
384 .mmap = NULL, 512 .mmap = NULL,
385}; 513};
386 514
515static struct class *tb_class;
516static struct device *tb_dev;
517
387static int __init sbprof_tb_init(void) 518static int __init sbprof_tb_init(void)
388{ 519{
520 struct device *dev;
521 struct class *tbc;
522 int err;
523
389 if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) { 524 if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
390 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n", 525 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
391 SBPROF_TB_MAJOR); 526 SBPROF_TB_MAJOR);
392 return -EIO; 527 return -EIO;
393 } 528 }
529
530 tbc = class_create(THIS_MODULE, "sb_tracebuffer");
531 if (IS_ERR(tbc)) {
532 err = PTR_ERR(tbc);
533 goto out_chrdev;
534 }
535
536 tb_class = tbc;
537
538 dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), "tb");
539 if (IS_ERR(dev)) {
540 err = PTR_ERR(dev);
541 goto out_class;
542 }
543 tb_dev = dev;
544
394 sbp.open = 0; 545 sbp.open = 0;
395 tb_period = zbbus_mhz * 10000LL; 546 tb_period = zbbus_mhz * 10000LL;
396 printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period); 547 pr_info(DEVNAME ": initialized - tb_period = %lld\n", tb_period);
548
397 return 0; 549 return 0;
550
551out_class:
552 class_destroy(tb_class);
553out_chrdev:
554 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
555
556 return err;
398} 557}
399 558
400static void __exit sbprof_tb_cleanup(void) 559static void __exit sbprof_tb_cleanup(void)
401{ 560{
561 device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
402 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME); 562 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
563 class_destroy(tb_class);
403} 564}
404 565
405module_init(sbprof_tb_init); 566module_init(sbprof_tb_init);
406module_exit(sbprof_tb_cleanup); 567module_exit(sbprof_tb_cleanup);
568
569MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
570MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
571MODULE_LICENSE("GPL");
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 1cb042eab720..87188f0f6fbe 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -16,6 +16,7 @@
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/module.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/reboot.h> 21#include <linux/reboot.h>
21#include <linux/string.h> 22#include <linux/string.h>
@@ -32,6 +33,7 @@ unsigned int soc_pass;
32unsigned int soc_type; 33unsigned int soc_type;
33unsigned int periph_rev; 34unsigned int periph_rev;
34unsigned int zbbus_mhz; 35unsigned int zbbus_mhz;
36EXPORT_SYMBOL(zbbus_mhz);
35 37
36static char *soc_str; 38static char *soc_str;
37static char *pass_str; 39static char *pass_str;