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-rw-r--r--arch/mips/sibyte/bcm1480/smp.c5
-rw-r--r--arch/mips/sibyte/bcm1480/time.c74
-rw-r--r--arch/mips/sibyte/sb1250/irq.c36
-rw-r--r--arch/mips/sibyte/sb1250/smp.c5
-rw-r--r--arch/mips/sibyte/sb1250/time.c104
-rw-r--r--arch/mips/sibyte/swarm/setup.c25
6 files changed, 82 insertions, 167 deletions
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index 6eac36d1b8c8..02b266a31c46 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -69,8 +69,9 @@ void bcm1480_smp_init(void)
69 69
70void bcm1480_smp_finish(void) 70void bcm1480_smp_finish(void)
71{ 71{
72 extern void bcm1480_time_init(void); 72 extern void sb1480_clockevent_init(void);
73 bcm1480_time_init(); 73
74 sb1480_clockevent_init();
74 local_irq_enable(); 75 local_irq_enable();
75} 76}
76 77
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index 5b4bfbbb5a24..c730744aa474 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -27,9 +27,8 @@
27 */ 27 */
28#include <linux/clockchips.h> 28#include <linux/clockchips.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/sched.h> 30#include <linux/percpu.h>
31#include <linux/spinlock.h> 31#include <linux/spinlock.h>
32#include <linux/kernel_stat.h>
33 32
34#include <asm/irq.h> 33#include <asm/irq.h>
35#include <asm/addrspace.h> 34#include <asm/addrspace.h>
@@ -101,25 +100,36 @@ static void sibyte_set_mode(enum clock_event_mode mode,
101 break; 100 break;
102 101
103 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
103 case CLOCK_EVT_MODE_RESUME:
104 ; 104 ;
105 } 105 }
106} 106}
107 107
108struct clock_event_device sibyte_hpt_clockevent = { 108static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
109 .name = "bcm1480-counter", 109{
110 .features = CLOCK_EVT_FEAT_PERIODIC, 110 unsigned int cpu = smp_processor_id();
111 .set_mode = sibyte_set_mode, 111 void __iomem *timer_init;
112 .shift = 32, 112 unsigned int cnt;
113 .irq = 0, 113 int res;
114}; 114
115 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
116 cnt = __raw_readq(timer_init);
117 cnt += delta;
118 __raw_writeq(cnt, timer_init);
119 res = ((long)(__raw_readq(timer_init) - cnt ) > 0) ? -ETIME : 0;
120
121 return res;
122}
123
124static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
115 125
116static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 126static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
117{ 127{
118 struct clock_event_device *cd = &sibyte_hpt_clockevent;
119 unsigned int cpu = smp_processor_id(); 128 unsigned int cpu = smp_processor_id();
129 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
120 130
121 /* Reset the timer */ 131 /* Reset the timer */
122 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 132 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
123 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 133 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
124 cd->event_handler(cd); 134 cd->event_handler(cd);
125 135
@@ -140,24 +150,21 @@ static struct irqaction sibyte_counter_irqaction = {
140 * called directly from irq_handler.S when IP[4] is set during an 150 * called directly from irq_handler.S when IP[4] is set during an
141 * interrupt 151 * interrupt
142 */ 152 */
143static void __init sb1480_clockevent_init(void) 153void __cpuinit sb1480_clockevent_init(void)
144{ 154{
145 unsigned int cpu = smp_processor_id(); 155 unsigned int cpu = smp_processor_id();
146 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 156 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
157 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
147 158
148 setup_irq(irq, &sibyte_counter_irqaction); 159 cd->name = "bcm1480-counter";
149} 160 cd->features = CLOCK_EVT_FEAT_PERIODIC |
161 CLOCK_EVT_MODE_ONESHOT;
162 cd->set_next_event = sibyte_next_event;
163 cd->set_mode = sibyte_set_mode;
164 cd->irq = irq;
165 clockevent_set_clock(cd, BCM1480_HPT_VALUE);
150 166
151void bcm1480_timer_interrupt(void) 167 setup_irq(irq, &sibyte_counter_irqaction);
152{
153 int cpu = smp_processor_id();
154 int irq = K_BCM1480_INT_TIMER_0 + cpu;
155
156 /* Reset the timer */
157 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
158 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
159
160 ll_timer_interrupt(irq);
161} 168}
162 169
163static cycle_t bcm1480_hpt_read(void) 170static cycle_t bcm1480_hpt_read(void)
@@ -168,9 +175,26 @@ static cycle_t bcm1480_hpt_read(void)
168 return (jiffies + 1) * (BCM1480_HPT_VALUE / HZ) - count; 175 return (jiffies + 1) * (BCM1480_HPT_VALUE / HZ) - count;
169} 176}
170 177
178struct clocksource bcm1480_clocksource = {
179 .name = "MIPS",
180 .rating = 200,
181 .read = bcm1480_hpt_read,
182 .mask = CLOCKSOURCE_MASK(32),
183 .shift = 32,
184 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
185};
186
187void __init sb1480_clocksource_init(void)
188{
189 struct clocksource *cs = &bcm1480_clocksource;
190
191 clocksource_set_clock(cs, BCM1480_HPT_VALUE);
192 clocksource_register(cs);
193}
194
171void __init bcm1480_hpt_setup(void) 195void __init bcm1480_hpt_setup(void)
172{ 196{
173 clocksource_mips.read = bcm1480_hpt_read;
174 mips_hpt_frequency = BCM1480_HPT_VALUE; 197 mips_hpt_frequency = BCM1480_HPT_VALUE;
198 sb1480_clocksource_init();
175 sb1480_clockevent_init(); 199 sb1480_clockevent_init();
176} 200}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 7659174819c6..500d17e84c09 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -400,43 +400,11 @@ static void sb1250_kgdb_interrupt(void)
400 400
401#endif /* CONFIG_KGDB */ 401#endif /* CONFIG_KGDB */
402 402
403static inline void sb1250_timer_interrupt(void)
404{
405 int cpu = smp_processor_id();
406 int irq = K_INT_TIMER_0 + cpu;
407
408 irq_enter();
409 kstat_this_cpu.irqs[irq]++;
410
411 write_seqlock(&xtime_lock);
412
413 /* ACK interrupt */
414 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
415 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
416
417 /*
418 * call the generic timer interrupt handling
419 */
420 do_timer(1);
421
422 write_sequnlock(&xtime_lock);
423
424 /*
425 * In UP mode, we call local_timer_interrupt() to do profiling
426 * and process accouting.
427 *
428 * In SMP mode, local_timer_interrupt() is invoked by appropriate
429 * low-level local timer interrupt handler.
430 */
431 local_timer_interrupt(irq);
432
433 irq_exit();
434}
435
436extern void sb1250_mailbox_interrupt(void); 403extern void sb1250_mailbox_interrupt(void);
437 404
438asmlinkage void plat_irq_dispatch(void) 405asmlinkage void plat_irq_dispatch(void)
439{ 406{
407 unsigned int cpu = smp_processor_id();
440 unsigned int pending; 408 unsigned int pending;
441 409
442 /* 410 /*
@@ -454,7 +422,7 @@ asmlinkage void plat_irq_dispatch(void)
454 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ 422 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
455 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 423 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
456 else if (pending & CAUSEF_IP4) 424 else if (pending & CAUSEF_IP4)
457 sb1250_timer_interrupt(); 425 do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
458 426
459#ifdef CONFIG_SMP 427#ifdef CONFIG_SMP
460 else if (pending & CAUSEF_IP3) 428 else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index c38e1f34460d..aaa4f30dda79 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -57,8 +57,9 @@ void sb1250_smp_init(void)
57 57
58void sb1250_smp_finish(void) 58void sb1250_smp_finish(void)
59{ 59{
60 extern void sb1250_time_init(void); 60 extern void sb1250_clockevent_init(void);
61 sb1250_time_init(); 61
62 sb1250_clockevent_init();
62 local_irq_enable(); 63 local_irq_enable();
63} 64}
64 65
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index fe11fed8e0d7..9ef54628bc9c 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -100,6 +100,7 @@ static void sibyte_set_mode(enum clock_event_mode mode,
100 break; 100 break;
101 101
102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
103 case CLOCK_EVT_MODE_RESUME:
103 ; 104 ;
104 } 105 }
105} 106}
@@ -144,79 +145,7 @@ static struct irqaction sibyte_irqaction = {
144 .name = "timer", 145 .name = "timer",
145}; 146};
146 147
147/* 148void __cpuinit sb1250_clockevent_init(void)
148 * The general purpose timer ticks at 1 Mhz independent if
149 * the rest of the system
150 */
151static void sibyte_set_mode(enum clock_event_mode mode,
152 struct clock_event_device *evt)
153{
154 unsigned int cpu = smp_processor_id();
155 void __iomem *timer_cfg, *timer_init;
156
157 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
158 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
159
160 switch (mode) {
161 case CLOCK_EVT_MODE_PERIODIC:
162 __raw_writeq(0, timer_cfg);
163 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
164 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
165 timer_cfg);
166 break;
167
168 case CLOCK_EVT_MODE_ONESHOT:
169 /* Stop the timer until we actually program a shot */
170 case CLOCK_EVT_MODE_SHUTDOWN:
171 __raw_writeq(0, timer_cfg);
172 break;
173
174 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
175 ;
176 }
177}
178
179static int
180sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
181{
182 unsigned int cpu = smp_processor_id();
183 void __iomem *timer_cfg, *timer_init;
184
185 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
186 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
187
188 __raw_writeq(0, timer_cfg);
189 __raw_writeq(delta, timer_init);
190 __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
191
192 return 0;
193}
194
195struct clock_event_device sibyte_hpt_clockevent = {
196 .name = "sb1250-counter",
197 .features = CLOCK_EVT_FEAT_PERIODIC,
198 .set_mode = sibyte_set_mode,
199 .set_next_event = sibyte_next_event,
200 .shift = 32,
201 .irq = 0,
202};
203
204static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
205{
206 struct clock_event_device *cd = &sibyte_hpt_clockevent;
207
208 cd->event_handler(cd);
209
210 return IRQ_HANDLED;
211}
212
213static struct irqaction sibyte_irqaction = {
214 .handler = sibyte_counter_handler,
215 .flags = IRQF_DISABLED | IRQF_PERCPU,
216 .name = "timer",
217};
218
219static void __init sb1250_clockevent_init(void)
220{ 149{
221 struct clock_event_device *cd = &sibyte_hpt_clockevent; 150 struct clock_event_device *cd = &sibyte_hpt_clockevent;
222 unsigned int cpu = smp_processor_id(); 151 unsigned int cpu = smp_processor_id();
@@ -249,12 +178,6 @@ static void __init sb1250_clockevent_init(void)
249 clockevents_register_device(cd); 178 clockevents_register_device(cd);
250} 179}
251 180
252void __init plat_time_init(void)
253{
254 sb1250_clocksource_init();
255 sb1250_clockevent_init();
256}
257
258/* 181/*
259 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 182 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
260 * again. 183 * again.
@@ -267,3 +190,26 @@ static cycle_t sb1250_hpt_read(void)
267 190
268 return SB1250_HPT_VALUE - count; 191 return SB1250_HPT_VALUE - count;
269} 192}
193
194struct clocksource bcm1250_clocksource = {
195 .name = "MIPS",
196 .rating = 200,
197 .read = sb1250_hpt_read,
198 .mask = CLOCKSOURCE_MASK(32),
199 .shift = 32,
200 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
201};
202
203void __init sb1250_clocksource_init(void)
204{
205 struct clocksource *cs = &bcm1250_clocksource;
206
207 clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
208 clocksource_register(cs);
209}
210
211void __init plat_time_init(void)
212{
213 sb1250_clocksource_init();
214 sb1250_clockevent_init();
215}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 8b3ef0e4cd55..080c966263b7 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -69,31 +69,6 @@ const char *get_system_type(void)
69 return "SiByte " SIBYTE_BOARD_NAME; 69 return "SiByte " SIBYTE_BOARD_NAME;
70} 70}
71 71
72void __init plat_time_init(void)
73{
74#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
75 /* Setup HPT */
76 sb1250_hpt_setup();
77#endif
78}
79
80void __init plat_timer_setup(struct irqaction *irq)
81{
82 /*
83 * we don't set up irqaction, because we will deliver timer
84 * interrupts through low-level (direct) meachanism.
85 */
86
87 /* We only need to setup the generic timer */
88#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
89 bcm1480_time_init();
90#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
91 sb1250_time_init();
92#else
93#error invalid SiByte board configuration
94#endif
95}
96
97int swarm_be_handler(struct pt_regs *regs, int is_fixup) 72int swarm_be_handler(struct pt_regs *regs, int is_fixup)
98{ 73{
99 if (!is_fixup && (regs->cp0_cause & 4)) { 74 if (!is_fixup && (regs->cp0_cause & 4)) {