12 files changed, 378 insertions, 153 deletions

diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index ec7a2cffacf0..e6b003ec6716 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -1,35 +1,41 @@
 config SIBYTE_SB1250
         bool
         select HW_HAS_PCI
-        select SIBYTE_HAS_LDT
+        select SIBYTE_ENABLE_LDT_IF_PCI
+        select SIBYTE_HAS_ZBUS_PROFILING
         select SIBYTE_SB1xxx_SOC
         select SYS_SUPPORTS_SMP
 
 config SIBYTE_BCM1120
         bool
         select SIBYTE_BCM112X
+        select SIBYTE_HAS_ZBUS_PROFILING
         select SIBYTE_SB1xxx_SOC
 
 config SIBYTE_BCM1125
         bool
         select HW_HAS_PCI
         select SIBYTE_BCM112X
+        select SIBYTE_HAS_ZBUS_PROFILING
         select SIBYTE_SB1xxx_SOC
 
 config SIBYTE_BCM1125H
         bool
         select HW_HAS_PCI
         select SIBYTE_BCM112X
-        select SIBYTE_HAS_LDT
+        select SIBYTE_ENABLE_LDT_IF_PCI
+        select SIBYTE_HAS_ZBUS_PROFILING
         select SIBYTE_SB1xxx_SOC
 
 config SIBYTE_BCM112X
         bool
         select SIBYTE_SB1xxx_SOC
+        select SIBYTE_HAS_ZBUS_PROFILING
 
 config SIBYTE_BCM1x80
         bool
         select HW_HAS_PCI
+        select SIBYTE_HAS_ZBUS_PROFILING
         select SIBYTE_SB1xxx_SOC
         select SYS_SUPPORTS_SMP
 
@@ -37,6 +43,7 @@ config SIBYTE_BCM1x55
         bool
         select HW_HAS_PCI
         select SIBYTE_SB1xxx_SOC
+        select SIBYTE_HAS_ZBUS_PROFILING
         select SYS_SUPPORTS_SMP
 
 config SIBYTE_SB1xxx_SOC
@@ -95,8 +102,10 @@ config CPU_SB1_PASS_2
 
 config SIBYTE_HAS_LDT
         bool
-        depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
-        default y
+
+config SIBYTE_ENABLE_LDT_IF_PCI
+        bool
+        select SIBYTE_HAS_LDT if PCI
 
 config SIMULATION
         bool "Running under simulation"
@@ -116,6 +125,7 @@ config SB1_CERR_STALL
 config SIBYTE_CFE
         bool "Booting from CFE"
         depends on SIBYTE_SB1xxx_SOC
+        select SYS_HAS_EARLY_PRINTK
         help
           Make use of the CFE API for enumerating available memory,
           controlling secondary CPUs, and possibly console output.
@@ -131,6 +141,7 @@ config SIBYTE_CFE_CONSOLE
 config SIBYTE_STANDALONE
         bool
         depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
+        select SYS_HAS_EARLY_PRINTK
         default y
 
 config SIBYTE_STANDALONE_RAM_SIZE
@@ -160,5 +171,8 @@ config SIBYTE_SB1250_PROF
         depends on SIBYTE_SB1xxx_SOC
 
 config SIBYTE_TBPROF
-        bool "Support for ZBbus profiling"
-        depends on SIBYTE_SB1xxx_SOC
+        tristate "Support for ZBbus profiling"
+        depends on SIBYTE_HAS_ZBUS_PROFILING
+
+config SIBYTE_HAS_ZBUS_PROFILING
+        bool
diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile
index 7b36ff3873b7..cdc4c56c3e29 100644
--- a/arch/mips/sibyte/bcm1480/Makefile
+++ b/arch/mips/sibyte/bcm1480/Makefile
@@ -1,5 +1,3 @@
 obj-y := setup.o irq.o time.o
 
 obj-$(CONFIG_SMP)                       += smp.o
-
-EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 1dc5d05d8962..ba0c4b776c85 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -141,11 +141,11 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
         unsigned long flags;
         unsigned int irq_dirty;
 
-        i = first_cpu(mask);
-        if (next_cpu(i, mask) <= NR_CPUS) {
+        if (cpus_weight(mask) != 1) {
                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
                 return;
         }
+        i = first_cpu(mask);
 
         /* Convert logical CPU to physical CPU */
         cpu = cpu_logical_map(i);
@@ -420,7 +420,7 @@ void __init arch_init_irq(void)
 #ifdef CONFIG_GDB_CONSOLE
                 register_gdb_console();
 #endif
-                prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
+                printk("Waiting for GDB on UART port %d\n", kgdb_port);
                 set_debug_traps();
                 breakpoint();
         }
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c
index 8236d0c48542..bdaac34ae708 100644
--- a/arch/mips/sibyte/bcm1480/setup.c
+++ b/arch/mips/sibyte/bcm1480/setup.c
@@ -69,7 +69,7 @@ static inline int sys_rev_decode(void)
                 break;
 
             default:
-                prom_printf("Unknown part type %x\n", part_type);
+                printk("Unknown part type %x\n", part_type);
                 ret = 1;
                 break;
         }
@@ -102,7 +102,7 @@ static inline int setup_bcm1x80_bcm1x55(void)
                 pass_str = "B0 (pass2)";
                 break;
             default:
-                prom_printf("Unknown %s rev %x\n", soc_str, soc_pass);
+                printk("Unknown %s rev %x\n", soc_str, soc_pass);
                 periph_rev = 1;
                 pass_str = "Unknown Revision";
                 break;
@@ -122,14 +122,14 @@ void bcm1480_setup(void)
         soc_pass = G_SYS_REVISION(sys_rev);
 
         if (sys_rev_decode()) {
-                prom_printf("Restart after failure to identify SiByte chip\n");
+                printk("Restart after failure to identify SiByte chip\n");
                 machine_restart(NULL);
         }
 
         plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
         zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
 
-        prom_printf("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n",
+        printk("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n",
                     soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
-        prom_printf("Board type: %s\n", get_system_type());
+        printk("Board type: %s\n", get_system_type());
 }
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index bf328277c775..6eac36d1b8c8 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void);
  * independent of board/firmware
  */
 
-static volatile void *mailbox_0_set_regs[] = {
+static void *mailbox_0_set_regs[] = {
         IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
         IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
         IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
         IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
 };
 
-static volatile void *mailbox_0_clear_regs[] = {
+static void *mailbox_0_clear_regs[] = {
         IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
         IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
         IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
         IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
 };
 
-static volatile void *mailbox_0_regs[] = {
+static void *mailbox_0_regs[] = {
         IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
         IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
         IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index 9e6099e69622..ae4a92c3e529 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -221,10 +221,10 @@ static int __init initrd_setup(char *str)
                 goto fail;
         }
         initrd_end = initrd_start + initrd_size;
-        prom_printf("Found initrd of %lx@%lx\n", initrd_size, initrd_start);
+        printk("Found initrd of %lx@%lx\n", initrd_size, initrd_start);
         return 1;
  fail:
-        prom_printf("Bad initrd argument.  Disabling initrd\n");
+        printk("Bad initrd argument.  Disabling initrd\n");
         initrd_start = 0;
         initrd_end = 0;
         return 1;
@@ -281,7 +281,7 @@ void __init prom_init(void)
         }
         if (cfe_eptseal != CFE_EPTSEAL) {
                 /* too early for panic to do any good */
-                prom_printf("CFE's entrypoint seal doesn't match. Spinning.");
+                printk("CFE's entrypoint seal doesn't match. Spinning.");
                 while (1) ;
         }
         cfe_init(cfe_handle, cfe_ept);
@@ -303,7 +303,7 @@ void __init prom_init(void)
                 } else {
                         /* The loader should have set the command line */
                         /* too early for panic to do any good */
-                        prom_printf("LINUX_CMDLINE not defined in cfe.");
+                        printk("LINUX_CMDLINE not defined in cfe.");
                         while (1) ;
                 }
         }
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
new file mode 100644
index 000000000000..8a06a4fb5212
--- /dev/null
+++ b/arch/mips/sibyte/common/Makefile
@@ -0,0 +1,5 @@
+obj-y :=
+
+obj-$(CONFIG_SIBYTE_TBPROF)             += sb_tbprof.o
+
+EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index 212547c57310..4fcdaa8ba514 100644
--- a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -1,6 +1,4 @@
 /*
- * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -14,10 +12,16 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
+ * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2007 MIPS Technologies, Inc.
+ *    written by Ralf Baechle <ralf@linux-mips.org>
  */
 
-#define SBPROF_TB_DEBUG 0
+#undef DEBUG
 
+#include <linux/device.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
@@ -27,24 +31,113 @@
 #include <linux/vmalloc.h>
 #include <linux/fs.h>
 #include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/smp_lock.h>
 #include <linux/wait.h>
-#include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/sibyte/sb1250.h>
+
+#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
+#include <asm/sibyte/bcm1480_regs.h>
+#include <asm/sibyte/bcm1480_scd.h>
+#include <asm/sibyte/bcm1480_int.h>
+#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
 #include <asm/sibyte/sb1250_regs.h>
 #include <asm/sibyte/sb1250_scd.h>
 #include <asm/sibyte/sb1250_int.h>
-#include <asm/sibyte/trace_prof.h>
+#else
+#error invalid SiByte UART configuation
+#endif
+
+#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
+#undef K_INT_TRACE_FREEZE
+#define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
+#undef K_INT_PERF_CNT
+#define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
+#endif
+
+#include <asm/system.h>
+#include <asm/uaccess.h>
 
-#define DEVNAME "bcm1250_tbprof"
+#define SBPROF_TB_MAJOR 240
+
+typedef u64 tb_sample_t[6*256];
+
+enum open_status {
+        SB_CLOSED,
+        SB_OPENING,
+        SB_OPEN
+};
+
+struct sbprof_tb {
+        wait_queue_head_t       tb_sync;
+        wait_queue_head_t       tb_read;
+        struct mutex            lock;
+        enum open_status        open;
+        tb_sample_t             *sbprof_tbbuf;
+        int                     next_tb_sample;
+
+        volatile int            tb_enable;
+        volatile int            tb_armed;
+
+};
 
 static struct sbprof_tb sbp;
 
+#define MAX_SAMPLE_BYTES (24*1024*1024)
+#define MAX_TBSAMPLE_BYTES (12*1024*1024)
+
+#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
+#define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
+#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
+
+/* ioctls */
+#define SBPROF_ZBSTART          _IOW('s', 0, int)
+#define SBPROF_ZBSTOP           _IOW('s', 1, int)
+#define SBPROF_ZBWAITFULL       _IOW('s', 2, int)
+
+/*
+ * Routines for using 40-bit SCD cycle counter
+ *
+ * Client responsible for either handling interrupts or making sure
+ * the cycles counter never saturates, e.g., by doing
+ * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
+ */
+
+/*
+ * Configures SCD counter 0 to count ZCLKs starting from val;
+ * Configures SCD counters1,2,3 to count nothing.
+ * Must not be called while gathering ZBbus profiles.
+ */
+
+#define zclk_timer_init(val) \
+  __asm__ __volatile__ (".set push;" \
+                        ".set mips64;" \
+                        "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
+                        "sd   %0, 0x10($8);"   /* write val to counter0 */ \
+                        "sd   %1, 0($8);"      /* config counter0 for zclks*/ \
+                        ".set pop" \
+                        : /* no outputs */ \
+                                                     /* enable, counter0 */ \
+                        : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
+                        : /* modifies */ "$8" )
+
+
+/* Reads SCD counter 0 and puts result in value
+   unsigned long long val; */
+#define zclk_get(val) \
+  __asm__ __volatile__ (".set push;" \
+                        ".set mips64;" \
+                        "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
+                        "ld   %0, 0x10($8);"   /* write val to counter0 */ \
+                        ".set pop" \
+                        : /* outputs */ "=r"(val) \
+                        : /* inputs */ \
+                        : /* modifies */ "$8" )
+
+#define DEVNAME "sb_tbprof"
+
 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
 
-/************************************************************************
+/*
  * Support for ZBbus sampling using the trace buffer
  *
  * We use the SCD performance counter interrupt, caused by a Zclk counter
@@ -55,28 +148,46 @@ static struct sbprof_tb sbp;
  *
  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
  *
- ************************************************************************/
+ */
 
-static u_int64_t tb_period;
+static u64 tb_period;
 
 static void arm_tb(void)
 {
-        u_int64_t scdperfcnt;
-        u_int64_t next = (1ULL << 40) - tb_period;
-        u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
-        /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
-           trigger start of trace.  XXX vary sampling period */
+        u64 scdperfcnt;
+        u64 next = (1ULL << 40) - tb_period;
+        u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
+
+        /*
+         * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
+         * trigger start of trace.  XXX vary sampling period
+         */
         __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
-        /* Unfortunately, in Pass 2 we must clear all counters to knock down
-           a previous interrupt request.  This means that bus profiling
-           requires ALL of the SCD perf counters. */
+
+        /*
+         * Unfortunately, in Pass 2 we must clear all counters to knock down
+         * a previous interrupt request.  This means that bus profiling
+         * requires ALL of the SCD perf counters.
+         */
+#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
+        __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
+                                                /* keep counters 0,2,3,4,5,6,7 as is */
+                     V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
+                     IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
+        __raw_writeq(
+                     M_SPC_CFG_ENABLE |         /* enable counting */
+                     M_SPC_CFG_CLEAR |          /* clear all counters */
+                     V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
+                     IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
+#else
         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
-                                                // keep counters 0,2,3 as is
-                     M_SPC_CFG_ENABLE |         // enable counting
-                     M_SPC_CFG_CLEAR |          // clear all counters
-                     V_SPC_CFG_SRC1(1),         // counter 1 counts cycles
+                                                /* keep counters 0,2,3 as is */
+                     M_SPC_CFG_ENABLE |         /* enable counting */
+                     M_SPC_CFG_CLEAR |          /* clear all counters */
+                     V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
                      IOADDR(A_SCD_PERF_CNT_CFG));
+#endif
         __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
         /* Reset the trace buffer */
         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
@@ -91,49 +202,51 @@ static void arm_tb(void)
 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
 {
         int i;
-        DBG(printk(DEVNAME ": tb_intr\n"));
+
+        pr_debug(DEVNAME ": tb_intr\n");
+
         if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
                 /* XXX should use XKPHYS to make writes bypass L2 */
-                u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
+                u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
                 /* Read out trace */
                 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
                              IOADDR(A_SCD_TRACE_CFG));
                 __asm__ __volatile__ ("sync" : : : "memory");
                 /* Loop runs backwards because bundles are read out in reverse order */
                 for (i = 256 * 6; i > 0; i -= 6) {
-                        // Subscripts decrease to put bundle in the order
-                        //   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
+                        /* Subscripts decrease to put bundle in the order */
+                        /*   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
                         p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t2 hi
+                        /* read t2 hi */
                         p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t2 lo
+                        /* read t2 lo */
                         p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t1 hi
+                        /* read t1 hi */
                         p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t1 lo
+                        /* read t1 lo */
                         p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t0 hi
+                        /* read t0 hi */
                         p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t0 lo
+                        /* read t0 lo */
                 }
                 if (!sbp.tb_enable) {
-                        DBG(printk(DEVNAME ": tb_intr shutdown\n"));
+                        pr_debug(DEVNAME ": tb_intr shutdown\n");
                         __raw_writeq(M_SCD_TRACE_CFG_RESET,
                                      IOADDR(A_SCD_TRACE_CFG));
                         sbp.tb_armed = 0;
-                        wake_up(&sbp.tb_sync);
+                        wake_up_interruptible(&sbp.tb_sync);
                 } else {
-                        arm_tb();       // knock down current interrupt and get another one later
+                        /* knock down current interrupt and get another one later */
+                        arm_tb();
                 }
         } else {
                 /* No more trace buffer samples */
-                DBG(printk(DEVNAME ": tb_intr full\n"));
+                pr_debug(DEVNAME ": tb_intr full\n");
                 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
                 sbp.tb_armed = 0;
-                if (!sbp.tb_enable) {
-                        wake_up(&sbp.tb_sync);
-                }
-                wake_up(&sbp.tb_read);
+                if (!sbp.tb_enable)
+                        wake_up_interruptible(&sbp.tb_sync);
+                wake_up_interruptible(&sbp.tb_read);
         }
         return IRQ_HANDLED;
 }
@@ -144,23 +257,30 @@ static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
         return IRQ_NONE;
 }
 
-int sbprof_zbprof_start(struct file *filp)
+/*
+ * Requires: Already called zclk_timer_init with a value that won't
+ *           saturate 40 bits.  No subsequent use of SCD performance counters
+ *           or trace buffer.
+ */
+
+static int sbprof_zbprof_start(struct file *filp)
 {
-        u_int64_t scdperfcnt;
+        u64 scdperfcnt;
+        int err;
 
-        if (sbp.tb_enable)
+        if (xchg(&sbp.tb_enable, 1))
                 return -EBUSY;
 
-        DBG(printk(DEVNAME ": starting\n"));
+        pr_debug(DEVNAME ": starting\n");
 
-        sbp.tb_enable = 1;
         sbp.next_tb_sample = 0;
         filp->f_pos = 0;
 
-        if (request_irq
-            (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) {
+        err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
+                           DEVNAME " trace freeze", &sbp);
+        if (err)
                 return -EBUSY;
-        }
+
         /* Make sure there isn't a perf-cnt interrupt waiting */
         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
         /* Disable and clear counters, override SRC_1 */
@@ -168,21 +288,30 @@ int sbprof_zbprof_start(struct file *filp)
                      M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
                      IOADDR(A_SCD_PERF_CNT_CFG));
 
-        /* We grab this interrupt to prevent others from trying to use
-           it, even though we don't want to service the interrupts
-           (they only feed into the trace-on-interrupt mechanism) */
-        if (request_irq
-            (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
+        /*
+         * We grab this interrupt to prevent others from trying to use
+         * it, even though we don't want to service the interrupts
+         * (they only feed into the trace-on-interrupt mechanism)
+         */
+        if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
                 free_irq(K_INT_TRACE_FREEZE, &sbp);
                 return -EBUSY;
         }
 
-        /* I need the core to mask these, but the interrupt mapper to
-           pass them through.  I am exploiting my knowledge that
-           cp0_status masks out IP[5]. krw */
+        /*
+         * I need the core to mask these, but the interrupt mapper to
+         *  pass them through.  I am exploiting my knowledge that
+         *  cp0_status masks out IP[5]. krw
+         */
+#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
+        __raw_writeq(K_BCM1480_INT_MAP_I3,
+                     IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
+                            ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
+#else
         __raw_writeq(K_INT_MAP_I3,
                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
                             (K_INT_PERF_CNT << 3)));
+#endif
 
         /* Initialize address traps */
         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
@@ -201,7 +330,7 @@ int sbprof_zbprof_start(struct file *filp)
         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 
         /* Initialize Trace Event 0-7 */
-        //                              when interrupt
+        /*                              when interrupt  */
         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
@@ -212,10 +341,10 @@ int sbprof_zbprof_start(struct file *filp)
         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
 
         /* Initialize Trace Sequence 0-7 */
-        //                                   Start on event 0 (interrupt)
+        /*                                   Start on event 0 (interrupt) */
         __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
                      IOADDR(A_SCD_TRACE_SEQUENCE_0));
-        //                        dsamp when d used | asamp when a used
+        /*                        dsamp when d used | asamp when a used */
         __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
                      K_SCD_TRSEQ_TRIGGER_ALL,
                      IOADDR(A_SCD_TRACE_SEQUENCE_1));
@@ -227,40 +356,47 @@ int sbprof_zbprof_start(struct file *filp)
         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
 
         /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
+#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
+        __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
+                     IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
+#else
         __raw_writeq(1ULL << K_INT_PERF_CNT,
                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
-
+#endif
         arm_tb();
 
-        DBG(printk(DEVNAME ": done starting\n"));
+        pr_debug(DEVNAME ": done starting\n");
 
         return 0;
 }
 
-int sbprof_zbprof_stop(void)
+static int sbprof_zbprof_stop(void)
 {
-        DEFINE_WAIT(wait);
-        DBG(printk(DEVNAME ": stopping\n"));
+        int err = 0;
+
+        pr_debug(DEVNAME ": stopping\n");
 
         if (sbp.tb_enable) {
+                /*
+                 * XXXKW there is a window here where the intr handler may run,
+                 * see the disable, and do the wake_up before this sleep
+                 * happens.
+                 */
+                pr_debug(DEVNAME ": wait for disarm\n");
+                err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
+                pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
+
+                if (err)
+                        return err;
+
                 sbp.tb_enable = 0;
-                /* XXXKW there is a window here where the intr handler
-                   may run, see the disable, and do the wake_up before
-                   this sleep happens. */
-                if (sbp.tb_armed) {
-                        DBG(printk(DEVNAME ": wait for disarm\n"));
-                        prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE);
-                        schedule();
-                        finish_wait(&sbp.tb_sync, &wait);
-                        DBG(printk(DEVNAME ": disarm complete\n"));
-                }
                 free_irq(K_INT_TRACE_FREEZE, &sbp);
                 free_irq(K_INT_PERF_CNT, &sbp);
         }
 
-        DBG(printk(DEVNAME ": done stopping\n"));
+        pr_debug(DEVNAME ": done stopping\n");
 
-        return 0;
+        return err;
 }
 
 static int sbprof_tb_open(struct inode *inode, struct file *filp)
@@ -268,22 +404,22 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp)
         int minor;
 
         minor = iminor(inode);
-        if (minor != 0) {
+        if (minor != 0)
                 return -ENODEV;
-        }
-        if (sbp.open) {
+
+        if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
                 return -EBUSY;
-        }
 
         memset(&sbp, 0, sizeof(struct sbprof_tb));
         sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
-        if (!sbp.sbprof_tbbuf) {
+        if (!sbp.sbprof_tbbuf)
                 return -ENOMEM;
-        }
         memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
         init_waitqueue_head(&sbp.tb_sync);
         init_waitqueue_head(&sbp.tb_read);
-        sbp.open = 1;
+        mutex_init(&sbp.lock);
+
+        sbp.open = SB_OPEN;
 
         return 0;
 }
@@ -293,17 +429,19 @@ static int sbprof_tb_release(struct inode *inode, struct file *filp)
         int minor;
 
         minor = iminor(inode);
-        if (minor != 0 || !sbp.open) {
+        if (minor != 0 || !sbp.open)
                 return -ENODEV;
-        }
 
-        if (sbp.tb_armed || sbp.tb_enable) {
+        mutex_lock(&sbp.lock);
+
+        if (sbp.tb_armed || sbp.tb_enable)
                 sbprof_zbprof_stop();
-        }
 
         vfree(sbp.sbprof_tbbuf);
         sbp.open = 0;
 
+        mutex_unlock(&sbp.lock);
+
         return 0;
 }
 
@@ -316,16 +454,29 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
         char *dest    =  buf;
         long  cur_off = *offp;
 
+        if (!access_ok(VERIFY_WRITE, buf, size))
+                return -EFAULT;
+
+        mutex_lock(&sbp.lock);
+
         count = 0;
         cur_sample = cur_off / TB_SAMPLE_SIZE;
         sample_off = cur_off % TB_SAMPLE_SIZE;
         sample_left = TB_SAMPLE_SIZE - sample_off;
+
         while (size && (cur_sample < sbp.next_tb_sample)) {
+                int err;
+
                 cur_count = size < sample_left ? size : sample_left;
                 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
-                copy_to_user(dest, src, cur_count);
-                DBG(printk(DEVNAME ": read from sample %d, %d bytes\n",
-                           cur_sample, cur_count));
+                err = __copy_to_user(dest, src, cur_count);
+                if (err) {
+                        *offp = cur_off + cur_count - err;
+                        mutex_unlock(&sbp.lock);
+                        return err;
+                }
+                pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
+                         cur_sample, cur_count);
                 size -= cur_count;
                 sample_left -= cur_count;
                 if (!sample_left) {
@@ -340,6 +491,7 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
                 count += cur_count;
         }
         *offp = cur_off;
+        mutex_unlock(&sbp.lock);
 
         return count;
 }
@@ -348,30 +500,36 @@ static long sbprof_tb_ioctl(struct file *filp,
                             unsigned int command,
                             unsigned long arg)
 {
-        int error = 0;
+        int err = 0;
 
-        lock_kernel();
         switch (command) {
         case SBPROF_ZBSTART:
-                error = sbprof_zbprof_start(filp);
+                mutex_lock(&sbp.lock);
+                err = sbprof_zbprof_start(filp);
+                mutex_unlock(&sbp.lock);
                 break;
+
         case SBPROF_ZBSTOP:
-                error = sbprof_zbprof_stop();
+                mutex_lock(&sbp.lock);
+                err = sbprof_zbprof_stop();
+                mutex_unlock(&sbp.lock);
+                break;
+
+        case SBPROF_ZBWAITFULL: {
+                err = wait_event_interruptible(sbp.tb_read, TB_FULL);
+                if (err)
+                        break;
+
+                err = put_user(TB_FULL, (int *) arg);
                 break;
-        case SBPROF_ZBWAITFULL:
-                DEFINE_WAIT(wait);
-                prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE);
-                schedule();
-                finish_wait(&sbp.tb_read, &wait);
-                /* XXXKW check if interrupted? */
-                return put_user(TB_FULL, (int *) arg);
+        }
+
         default:
-                error = -EINVAL;
+                err = -EINVAL;
                 break;
         }
-        unlock_kernel();
 
-        return error;
+        return err;
 }
 
 static const struct file_operations sbprof_tb_fops = {
@@ -384,23 +542,60 @@ static const struct file_operations sbprof_tb_fops = {
         .mmap           = NULL,
 };
 
+static struct class *tb_class;
+static struct device *tb_dev;
+
 static int __init sbprof_tb_init(void)
 {
+        struct device *dev;
+        struct class *tbc;
+        int err;
+
         if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
                 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
                        SBPROF_TB_MAJOR);
                 return -EIO;
         }
+
+        tbc = class_create(THIS_MODULE, "sb_tracebuffer");
+        if (IS_ERR(tbc)) {
+                err = PTR_ERR(tbc);
+                goto out_chrdev;
+        }
+
+        tb_class = tbc;
+
+        dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), "tb");
+        if (IS_ERR(dev)) {
+                err = PTR_ERR(dev);
+                goto out_class;
+        }
+        tb_dev = dev;
+
         sbp.open = 0;
         tb_period = zbbus_mhz * 10000LL;
-        printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period);
+        pr_info(DEVNAME ": initialized - tb_period = %lld\n",
+                (long long) tb_period);
         return 0;
+
+out_class:
+        class_destroy(tb_class);
+out_chrdev:
+        unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
+
+        return err;
 }
 
 static void __exit sbprof_tb_cleanup(void)
 {
+        device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
+        class_destroy(tb_class);
 }
 
 module_init(sbprof_tb_init);
 module_exit(sbprof_tb_cleanup);
+
+MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
+MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index a2fdbd62f8ac..df662c61473a 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -1,8 +1,5 @@
 obj-y := setup.o irq.o time.o
 
 obj-$(CONFIG_SMP)                       += smp.o
-obj-$(CONFIG_SIBYTE_TBPROF)             += bcm1250_tbprof.o
 obj-$(CONFIG_SIBYTE_STANDALONE)         += prom.o
 obj-$(CONFIG_SIBYTE_BUS_WATCHER)        += bus_watcher.o
-
-EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 148239446e6e..0e6a13c0bd0e 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -421,7 +421,7 @@ asmlinkage void plat_irq_dispatch(void)
          * blasting the high 32 bits.
          */
 
-        pending = read_c0_cause() & read_c0_status();
+        pending = read_c0_cause() & read_c0_status() & ST0_IM;
 
 #ifdef CONFIG_SIBYTE_SB1250_PROF
         if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index d0ee1d5b8223..f4a6169aa0a4 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -16,6 +16,7 @@
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  */
 #include <linux/init.h>
+#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/reboot.h>
 #include <linux/string.h>
@@ -32,6 +33,7 @@ unsigned int soc_pass;
 unsigned int soc_type;
 unsigned int periph_rev;
 unsigned int zbbus_mhz;
+EXPORT_SYMBOL(zbbus_mhz);
 
 static char *soc_str;
 static char *pass_str;
@@ -67,7 +69,7 @@ static int __init sys_rev_decode(void)
                 ret = setup_bcm112x();
                 break;
         default:
-                prom_printf("Unknown SOC type %x\n", soc_type);
+                printk("Unknown SOC type %x\n", soc_type);
                 ret = 1;
                 break;
         }
@@ -112,7 +114,7 @@ static int __init setup_bcm1250(void)
                         pass_str = "A0-A6";
                         war_pass = K_SYS_REVISION_BCM1250_PASS2;
                 } else {
-                        prom_printf("Unknown BCM1250 rev %x\n", soc_pass);
+                        printk("Unknown BCM1250 rev %x\n", soc_pass);
                         ret = 1;
                 }
                 break;
@@ -139,8 +141,20 @@ static int __init setup_bcm112x(void)
                 periph_rev = 3;
                 pass_str = "A2";
                 break;
+        case K_SYS_REVISION_BCM112x_A3:
+                periph_rev = 3;
+                pass_str = "A3";
+                break;
+        case K_SYS_REVISION_BCM112x_A4:
+                periph_rev = 3;
+                pass_str = "A4";
+                break;
+        case K_SYS_REVISION_BCM112x_B0:
+                periph_rev = 3;
+                pass_str = "B0";
+                break;
         default:
-                prom_printf("Unknown %s rev %x\n", soc_str, soc_pass);
+                printk("Unknown %s rev %x\n", soc_str, soc_pass);
                 ret = 1;
         }
         return ret;
@@ -158,21 +172,21 @@ void __init sb1250_setup(void)
         soc_pass = G_SYS_REVISION(sys_rev);
 
         if (sys_rev_decode()) {
-                prom_printf("Restart after failure to identify SiByte chip\n");
+                printk("Restart after failure to identify SiByte chip\n");
                 machine_restart(NULL);
         }
 
         plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
         zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
 
-        prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",
+        printk("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",
                     soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
-        prom_printf("Board type: %s\n", get_system_type());
+        printk("Board type: %s\n", get_system_type());
 
         switch (war_pass) {
         case K_SYS_REVISION_BCM1250_PASS1:
 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
-                prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
+                printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
                             "and the kernel doesn't have the proper "
                             "workarounds compiled in. @@@@\n");
                 bad_config = 1;
@@ -182,27 +196,27 @@ void __init sb1250_setup(void)
                 /* Pass 2 - easiest as default for now - so many numbers */
 #if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \
     !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
-                prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the "
+                printk("@@@@ This is a BCM1250 A3-A10 board, and the "
                             "kernel doesn't have the proper workarounds "
                             "compiled in. @@@@\n");
                 bad_config = 1;
 #endif
 #ifdef CONFIG_CPU_HAS_PREFETCH
-                prom_printf("@@@@ Prefetches may be enabled in this kernel, "
+                printk("@@@@ Prefetches may be enabled in this kernel, "
                             "but are buggy on this board.  @@@@\n");
                 bad_config = 1;
 #endif
                 break;
         case K_SYS_REVISION_BCM1250_PASS2_2:
 #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
-                prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the "
+                printk("@@@@ This is a BCM1250 B1/B2. board, and the "
                             "kernel doesn't have the proper workarounds "
                             "compiled in. @@@@\n");
                 bad_config = 1;
 #endif
 #if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \
     !defined(CONFIG_CPU_HAS_PREFETCH)
-                prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is "
+                printk("@@@@ This is a BCM1250 B1/B2, but the kernel is "
                             "conservatively configured for an 'A' stepping. "
                             "@@@@\n");
 #endif
@@ -211,7 +225,7 @@ void __init sb1250_setup(void)
                 break;
         }
         if (bad_config) {
-                prom_printf("Invalid configuration for this chip.\n");
+                printk("Invalid configuration for this chip.\n");
                 machine_restart(NULL);
         }
 }
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index defa1f1452ad..83572d8f3e14 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -169,17 +169,19 @@ void __init plat_mem_setup(void)
 #define LEDS_PHYS MLEDS_PHYS
 #endif
 
-#define setled(index, c) \
-  ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c)
 void setleds(char *str)
 {
+        void *reg;
         int i;
+
         for (i = 0; i < 4; i++) {
-                if (!str[i]) {
-                        setled(i, ' ');
-                } else {
-                        setled(i, str[i]);
-                }
+                reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3);
+
+                if (!str[i])
+                        writeb(' ', reg);
+                else
+                        writeb(str[i], reg);
         }
 }
-#endif
+
+#endif /* LEDS_PHYS */