diff options
Diffstat (limited to 'arch/mips/sibyte/swarm')
-rw-r--r-- | arch/mips/sibyte/swarm/rtc_m41t81.c | 10 | ||||
-rw-r--r-- | arch/mips/sibyte/swarm/setup.c | 2 |
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c index 0e633ee8d83c..a686bb716ec6 100644 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c | |||
@@ -128,7 +128,7 @@ static int m41t81_write(uint8_t addr, int b) | |||
128 | /* Clear error bit by writing a 1 */ | 128 | /* Clear error bit by writing a 1 */ |
129 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 129 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
130 | return -1; | 130 | return -1; |
131 | } | 131 | } |
132 | 132 | ||
133 | /* read the same byte again to make sure it is written */ | 133 | /* read the same byte again to make sure it is written */ |
134 | bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, | 134 | bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, |
@@ -136,7 +136,7 @@ static int m41t81_write(uint8_t addr, int b) | |||
136 | 136 | ||
137 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 137 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
138 | ; | 138 | ; |
139 | 139 | ||
140 | return 0; | 140 | return 0; |
141 | } | 141 | } |
142 | 142 | ||
@@ -148,13 +148,13 @@ int m41t81_set_time(unsigned long t) | |||
148 | 148 | ||
149 | /* | 149 | /* |
150 | * Note the write order matters as it ensures the correctness. | 150 | * Note the write order matters as it ensures the correctness. |
151 | * When we write sec, 10th sec is clear. It is reasonable to | 151 | * When we write sec, 10th sec is clear. It is reasonable to |
152 | * believe we should finish writing min within a second. | 152 | * believe we should finish writing min within a second. |
153 | */ | 153 | */ |
154 | 154 | ||
155 | tm.tm_sec = BIN2BCD(tm.tm_sec); | 155 | tm.tm_sec = BIN2BCD(tm.tm_sec); |
156 | m41t81_write(M41T81REG_SC, tm.tm_sec); | 156 | m41t81_write(M41T81REG_SC, tm.tm_sec); |
157 | 157 | ||
158 | tm.tm_min = BIN2BCD(tm.tm_min); | 158 | tm.tm_min = BIN2BCD(tm.tm_min); |
159 | m41t81_write(M41T81REG_MN, tm.tm_min); | 159 | m41t81_write(M41T81REG_MN, tm.tm_min); |
160 | 160 | ||
@@ -187,7 +187,7 @@ unsigned long m41t81_get_time(void) | |||
187 | { | 187 | { |
188 | unsigned int year, mon, day, hour, min, sec; | 188 | unsigned int year, mon, day, hour, min, sec; |
189 | 189 | ||
190 | /* | 190 | /* |
191 | * min is valid if two reads of sec are the same. | 191 | * min is valid if two reads of sec are the same. |
192 | */ | 192 | */ |
193 | for (;;) { | 193 | for (;;) { |
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 4742e4fc89f7..4daeaa413def 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c | |||
@@ -98,7 +98,7 @@ static int __init swarm_setup(void) | |||
98 | rtc_get_time = xicor_get_time; | 98 | rtc_get_time = xicor_get_time; |
99 | rtc_set_time = xicor_set_time; | 99 | rtc_set_time = xicor_set_time; |
100 | } | 100 | } |
101 | 101 | ||
102 | if (m41t81_probe()) { | 102 | if (m41t81_probe()) { |
103 | printk("swarm setup: M41T81 RTC detected.\n"); | 103 | printk("swarm setup: M41T81 RTC detected.\n"); |
104 | rtc_get_time = m41t81_get_time; | 104 | rtc_get_time = m41t81_get_time; |