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-rw-r--r--arch/mips/sibyte/swarm/rtc_m41t81.c47
-rw-r--r--arch/mips/sibyte/swarm/rtc_xicor1241.c42
-rw-r--r--arch/mips/sibyte/swarm/time.c44
3 files changed, 67 insertions, 66 deletions
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c
index a686bb716ec6..5b4fc26c1b36 100644
--- a/arch/mips/sibyte/swarm/rtc_m41t81.c
+++ b/arch/mips/sibyte/swarm/rtc_m41t81.c
@@ -82,59 +82,60 @@
82#define M41T81REG_SQW 0x13 /* square wave register */ 82#define M41T81REG_SQW 0x13 /* square wave register */
83 83
84#define M41T81_CCR_ADDRESS 0x68 84#define M41T81_CCR_ADDRESS 0x68
85#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) 85
86#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
86 87
87static int m41t81_read(uint8_t addr) 88static int m41t81_read(uint8_t addr)
88{ 89{
89 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 90 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
90 ; 91 ;
91 92
92 bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); 93 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
93 bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), 94 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
94 SMB_CSR(R_SMB_START)); 95 SMB_CSR(R_SMB_START));
95 96
96 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 97 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
97 ; 98 ;
98 99
99 bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), 100 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
100 SMB_CSR(R_SMB_START)); 101 SMB_CSR(R_SMB_START));
101 102
102 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 103 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
103 ; 104 ;
104 105
105 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 106 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
106 /* Clear error bit by writing a 1 */ 107 /* Clear error bit by writing a 1 */
107 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 108 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
108 return -1; 109 return -1;
109 } 110 }
110 111
111 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 112 return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
112} 113}
113 114
114static int m41t81_write(uint8_t addr, int b) 115static int m41t81_write(uint8_t addr, int b)
115{ 116{
116 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 117 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
117 ; 118 ;
118 119
119 bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); 120 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
120 bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); 121 __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
121 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, 122 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
122 SMB_CSR(R_SMB_START)); 123 SMB_CSR(R_SMB_START));
123 124
124 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 125 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
125 ; 126 ;
126 127
127 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 128 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
128 /* Clear error bit by writing a 1 */ 129 /* Clear error bit by writing a 1 */
129 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 130 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
130 return -1; 131 return -1;
131 } 132 }
132 133
133 /* read the same byte again to make sure it is written */ 134 /* read the same byte again to make sure it is written */
134 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, 135 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
135 SMB_CSR(R_SMB_START)); 136 SMB_CSR(R_SMB_START));
136 137
137 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 138 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
138 ; 139 ;
139 140
140 return 0; 141 return 0;
diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c
index 981d21f16e64..d9ff9323f24e 100644
--- a/arch/mips/sibyte/swarm/rtc_xicor1241.c
+++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c
@@ -57,52 +57,52 @@
57 57
58#define X1241_CCR_ADDRESS 0x6F 58#define X1241_CCR_ADDRESS 0x6F
59 59
60#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) 60#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
61 61
62static int xicor_read(uint8_t addr) 62static int xicor_read(uint8_t addr)
63{ 63{
64 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 64 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
65 ; 65 ;
66 66
67 bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); 67 __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
68 bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); 68 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
69 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), 69 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
70 SMB_CSR(R_SMB_START)); 70 SMB_CSR(R_SMB_START));
71 71
72 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 72 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
73 ; 73 ;
74 74
75 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), 75 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
76 SMB_CSR(R_SMB_START)); 76 SMB_CSR(R_SMB_START));
77 77
78 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 78 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
79 ; 79 ;
80 80
81 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 81 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
82 /* Clear error bit by writing a 1 */ 82 /* Clear error bit by writing a 1 */
83 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 83 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
84 return -1; 84 return -1;
85 } 85 }
86 86
87 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 87 return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
88} 88}
89 89
90static int xicor_write(uint8_t addr, int b) 90static int xicor_write(uint8_t addr, int b)
91{ 91{
92 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 92 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
93 ; 93 ;
94 94
95 bus_writeq(addr, SMB_CSR(R_SMB_CMD)); 95 __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
96 bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); 96 __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
97 bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, 97 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
98 SMB_CSR(R_SMB_START)); 98 SMB_CSR(R_SMB_START));
99 99
100 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 100 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
101 ; 101 ;
102 102
103 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 103 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
104 /* Clear error bit by writing a 1 */ 104 /* Clear error bit by writing a 1 */
105 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 105 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
106 return -1; 106 return -1;
107 } else { 107 } else {
108 return 0; 108 return 0;
diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c
index c1f1a9defeeb..97c73c793c35 100644
--- a/arch/mips/sibyte/swarm/time.c
+++ b/arch/mips/sibyte/swarm/time.c
@@ -79,48 +79,48 @@ static unsigned int usec_bias = 0;
79 79
80static int xicor_read(uint8_t addr) 80static int xicor_read(uint8_t addr)
81{ 81{
82 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 82 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
83 ; 83 ;
84 84
85 bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); 85 __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
86 bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); 86 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
87 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), 87 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
88 SMB_CSR(R_SMB_START)); 88 SMB_CSR(R_SMB_START));
89 89
90 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 90 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
91 ; 91 ;
92 92
93 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), 93 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
94 SMB_CSR(R_SMB_START)); 94 SMB_CSR(R_SMB_START));
95 95
96 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 96 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
97 ; 97 ;
98 98
99 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 99 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
100 /* Clear error bit by writing a 1 */ 100 /* Clear error bit by writing a 1 */
101 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 101 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
102 return -1; 102 return -1;
103 } 103 }
104 104
105 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 105 return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
106} 106}
107 107
108static int xicor_write(uint8_t addr, int b) 108static int xicor_write(uint8_t addr, int b)
109{ 109{
110 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 110 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
111 ; 111 ;
112 112
113 bus_writeq(addr, SMB_CSR(R_SMB_CMD)); 113 __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
114 bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); 114 __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
115 bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, 115 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
116 SMB_CSR(R_SMB_START)); 116 SMB_CSR(R_SMB_START));
117 117
118 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 118 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
119 ; 119 ;
120 120
121 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 121 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
122 /* Clear error bit by writing a 1 */ 122 /* Clear error bit by writing a 1 */
123 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 123 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
124 return -1; 124 return -1;
125 } else { 125 } else {
126 return 0; 126 return 0;
@@ -228,8 +228,8 @@ void __init swarm_time_init(void)
228 /* Establish communication with the Xicor 1241 RTC */ 228 /* Establish communication with the Xicor 1241 RTC */
229 /* XXXKW how do I share the SMBus with the I2C subsystem? */ 229 /* XXXKW how do I share the SMBus with the I2C subsystem? */
230 230
231 bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); 231 __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
232 bus_writeq(0, SMB_CSR(R_SMB_CONTROL)); 232 __raw_writeq(0, SMB_CSR(R_SMB_CONTROL));
233 233
234 if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { 234 if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
235 printk("x1241: couldn't detect on SWARM SMBus 1\n"); 235 printk("x1241: couldn't detect on SWARM SMBus 1\n");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 00:39:59 -0500