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Diffstat (limited to 'arch/mips/sibyte/sb1250/irq.c')
-rw-r--r--arch/mips/sibyte/sb1250/irq.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 340aaf626659..fca0cdb99509 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -264,7 +264,7 @@ void __init arch_init_irq(void)
264 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + 264 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
265 (K_INT_MBOX_0 << 3))); 265 (K_INT_MBOX_0 << 3)));
266 266
267 /* Clear the mailboxes. The firmware may leave them dirty */ 267 /* Clear the mailboxes. The firmware may leave them dirty */
268 __raw_writeq(0xffffffffffffffffULL, 268 __raw_writeq(0xffffffffffffffffULL,
269 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); 269 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
270 __raw_writeq(0xffffffffffffffffULL, 270 __raw_writeq(0xffffffffffffffffULL,
@@ -277,7 +277,7 @@ void __init arch_init_irq(void)
277 277
278 /* 278 /*
279 * Note that the timer interrupts are also mapped, but this is 279 * Note that the timer interrupts are also mapped, but this is
280 * done in sb1250_time_init(). Also, the profiling driver 280 * done in sb1250_time_init(). Also, the profiling driver
281 * does its own management of IP7. 281 * does its own management of IP7.
282 */ 282 */
283 283
@@ -294,7 +294,7 @@ static inline void dispatch_ip2(void)
294 294
295 /* 295 /*
296 * Default...we've hit an IP[2] interrupt, which means we've got to 296 * Default...we've hit an IP[2] interrupt, which means we've got to
297 * check the 1250 interrupt registers to figure out what to do. Need 297 * check the 1250 interrupt registers to figure out what to do. Need
298 * to detect which CPU we're on, now that smp_affinity is supported. 298 * to detect which CPU we're on, now that smp_affinity is supported.
299 */ 299 */
300 mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu, 300 mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
@@ -323,7 +323,7 @@ asmlinkage void plat_irq_dispatch(void)
323 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ 323 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
324 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 324 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
325 else if (pending & CAUSEF_IP4) 325 else if (pending & CAUSEF_IP4)
326 do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */ 326 do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
327 327
328#ifdef CONFIG_SMP 328#ifdef CONFIG_SMP
329 else if (pending & CAUSEF_IP3) 329 else if (pending & CAUSEF_IP3)