1 files changed, 161 insertions, 0 deletions

diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
new file mode 100644
index 000000000000..de46f62ac462
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+++ b/arch/mips/sibyte/Kconfig
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+config SIBYTE_SB1250
+        bool
+        select HW_HAS_PCI
+        select SIBYTE_HAS_LDT
+        select SIBYTE_SB1xxx_SOC
+
+config SIBYTE_BCM1120
+        bool
+        select SIBYTE_BCM112X
+        select SIBYTE_SB1xxx_SOC
+
+config SIBYTE_BCM1125
+        bool
+        select HW_HAS_PCI
+        select SIBYTE_BCM112X
+        select SIBYTE_SB1xxx_SOC
+
+config SIBYTE_BCM1125H
+        bool
+        select HW_HAS_PCI
+        select SIBYTE_BCM112X
+        select SIBYTE_HAS_LDT
+        select SIBYTE_SB1xxx_SOC
+
+config SIBYTE_BCM112X
+        bool
+        select SIBYTE_SB1xxx_SOC
+
+config SIBYTE_BCM1x80
+        bool
+        select HW_HAS_PCI
+        select SIBYTE_SB1xxx_SOC
+
+config SIBYTE_BCM1x55
+        bool
+        select HW_HAS_PCI
+        select SIBYTE_SB1xxx_SOC
+
+config SIBYTE_SB1xxx_SOC
+        bool
+        depends on EXPERIMENTAL
+        select DMA_COHERENT
+        select SIBYTE_CFE
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_64BIT_KERNEL
+
+choice
+        prompt "SiByte SOC Stepping"
+        depends on SIBYTE_SB1xxx_SOC
+
+config CPU_SB1_PASS_1
+        bool "1250 Pass1"
+        depends on SIBYTE_SB1250
+        select CPU_HAS_PREFETCH
+
+config CPU_SB1_PASS_2_1250
+        bool "1250 An"
+        depends on SIBYTE_SB1250
+        select CPU_SB1_PASS_2
+        help
+          Also called BCM1250 Pass 2
+
+config CPU_SB1_PASS_2_2
+        bool "1250 Bn"
+        depends on SIBYTE_SB1250
+        select CPU_HAS_PREFETCH
+        help
+          Also called BCM1250 Pass 2.2
+
+config CPU_SB1_PASS_4
+        bool "1250 Cn"
+        depends on SIBYTE_SB1250
+        select CPU_HAS_PREFETCH
+        help
+          Also called BCM1250 Pass 3
+
+config CPU_SB1_PASS_2_112x
+        bool "112x Hybrid"
+        depends on SIBYTE_BCM112X
+        select CPU_SB1_PASS_2
+
+config CPU_SB1_PASS_3
+        bool "112x An"
+        depends on SIBYTE_BCM112X
+        select CPU_HAS_PREFETCH
+
+endchoice
+
+config CPU_SB1_PASS_2
+        bool
+
+config SIBYTE_HAS_LDT
+        bool
+        depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
+        default y
+
+config SIMULATION
+        bool "Running under simulation"
+        depends on SIBYTE_SB1xxx_SOC
+        help
+          Build a kernel suitable for running under the GDB simulator.
+          Primarily adjusts the kernel's notion of time.
+
+config CONFIG_SB1_CEX_ALWAYS_FATAL
+        bool "All cache exceptions considered fatal (no recovery attempted)"
+        depends on SIBYTE_SB1xxx_SOC
+
+config CONFIG_SB1_CERR_STALL
+        bool "Stall (rather than panic) on fatal cache error"
+        depends on SIBYTE_SB1xxx_SOC
+
+config SIBYTE_CFE
+        bool "Booting from CFE"
+        depends on SIBYTE_SB1xxx_SOC
+        help
+          Make use of the CFE API for enumerating available memory,
+          controlling secondary CPUs, and possibly console output.
+
+config SIBYTE_CFE_CONSOLE
+        bool "Use firmware console"
+        depends on SIBYTE_CFE
+        help
+          Use the CFE API's console write routines during boot.  Other console
+          options (VT console, sb1250 duart console, etc.) should not be
+          configured.
+
+config SIBYTE_STANDALONE
+        bool
+        depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
+        default y
+
+config SIBYTE_STANDALONE_RAM_SIZE
+        int "Memory size (in megabytes)"
+        depends on SIBYTE_STANDALONE
+        default "32"
+
+config SIBYTE_BUS_WATCHER
+        bool "Support for Bus Watcher statistics"
+        depends on SIBYTE_SB1xxx_SOC
+        help
+          Handle and keep statistics on the bus error interrupts (COR_ECC,
+          BAD_ECC, IO_BUS).
+
+config SIBYTE_BW_TRACE
+        bool "Capture bus trace before bus error"
+        depends on SIBYTE_BUS_WATCHER
+        help
+          Run a continuous bus trace, dumping the raw data as soon as
+          a ZBbus error is detected.  Cannot work if ZBbus profiling
+          is turned on, and also will interfere with JTAG-based trace
+          buffer activity.  Raw buffer data is dumped to console, and
+          must be processed off-line.
+
+config SIBYTE_SB1250_PROF
+        bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
+        depends on SIBYTE_SB1xxx_SOC
+
+config SIBYTE_TBPROF
+        bool "Support for ZBbus profiling"
+        depends on SIBYTE_SB1xxx_SOC