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Diffstat (limited to 'arch/mips/sgi-ip32/ip32-irq.c')
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c40
1 files changed, 24 insertions, 16 deletions
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index e0a3ce4a8d48..c65ea76d56c7 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -451,43 +451,51 @@ void __init arch_init_irq(void)
451 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { 451 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
452 switch (irq) { 452 switch (irq) {
453 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: 453 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
454 set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, 454 irq_set_chip_and_handler_name(irq,
455 handle_level_irq, "level"); 455 &ip32_mace_interrupt,
456 handle_level_irq,
457 "level");
456 break; 458 break;
457 459
458 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: 460 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
459 set_irq_chip_and_handler_name(irq, 461 irq_set_chip_and_handler_name(irq,
460 &ip32_macepci_interrupt, handle_level_irq, 462 &ip32_macepci_interrupt,
461 "level"); 463 handle_level_irq,
464 "level");
462 break; 465 break;
463 466
464 case CRIME_CPUERR_IRQ: 467 case CRIME_CPUERR_IRQ:
465 case CRIME_MEMERR_IRQ: 468 case CRIME_MEMERR_IRQ:
466 set_irq_chip_and_handler_name(irq, 469 irq_set_chip_and_handler_name(irq,
467 &crime_level_interrupt, handle_level_irq, 470 &crime_level_interrupt,
468 "level"); 471 handle_level_irq,
472 "level");
469 break; 473 break;
470 474
471 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: 475 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
472 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: 476 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
473 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: 477 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
474 case CRIME_VICE_IRQ: 478 case CRIME_VICE_IRQ:
475 set_irq_chip_and_handler_name(irq, 479 irq_set_chip_and_handler_name(irq,
476 &crime_edge_interrupt, handle_edge_irq, "edge"); 480 &crime_edge_interrupt,
481 handle_edge_irq,
482 "edge");
477 break; 483 break;
478 484
479 case MACEISA_PARALLEL_IRQ: 485 case MACEISA_PARALLEL_IRQ:
480 case MACEISA_SERIAL1_TDMAPR_IRQ: 486 case MACEISA_SERIAL1_TDMAPR_IRQ:
481 case MACEISA_SERIAL2_TDMAPR_IRQ: 487 case MACEISA_SERIAL2_TDMAPR_IRQ:
482 set_irq_chip_and_handler_name(irq, 488 irq_set_chip_and_handler_name(irq,
483 &ip32_maceisa_edge_interrupt, handle_edge_irq, 489 &ip32_maceisa_edge_interrupt,
484 "edge"); 490 handle_edge_irq,
491 "edge");
485 break; 492 break;
486 493
487 default: 494 default:
488 set_irq_chip_and_handler_name(irq, 495 irq_set_chip_and_handler_name(irq,
489 &ip32_maceisa_level_interrupt, handle_level_irq, 496 &ip32_maceisa_level_interrupt,
490 "level"); 497 handle_level_irq,
498 "level");
491 break; 499 break;
492 } 500 }
493 } 501 }