diff options
Diffstat (limited to 'arch/mips/sgi-ip32/ip32-irq.c')
-rw-r--r-- | arch/mips/sgi-ip32/ip32-irq.c | 63 |
1 files changed, 45 insertions, 18 deletions
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index 9cb28cd20ad8..83a0b3c359da 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c | |||
@@ -323,16 +323,11 @@ static void mask_and_ack_maceisa_irq(unsigned int irq) | |||
323 | { | 323 | { |
324 | unsigned long mace_int; | 324 | unsigned long mace_int; |
325 | 325 | ||
326 | switch (irq) { | 326 | /* edge triggered */ |
327 | case MACEISA_PARALLEL_IRQ: | 327 | mace_int = mace->perif.ctrl.istat; |
328 | case MACEISA_SERIAL1_TDMAPR_IRQ: | 328 | mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); |
329 | case MACEISA_SERIAL2_TDMAPR_IRQ: | 329 | mace->perif.ctrl.istat = mace_int; |
330 | /* edge triggered */ | 330 | |
331 | mace_int = mace->perif.ctrl.istat; | ||
332 | mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); | ||
333 | mace->perif.ctrl.istat = mace_int; | ||
334 | break; | ||
335 | } | ||
336 | disable_maceisa_irq(irq); | 331 | disable_maceisa_irq(irq); |
337 | } | 332 | } |
338 | 333 | ||
@@ -342,7 +337,16 @@ static void end_maceisa_irq(unsigned irq) | |||
342 | enable_maceisa_irq(irq); | 337 | enable_maceisa_irq(irq); |
343 | } | 338 | } |
344 | 339 | ||
345 | static struct irq_chip ip32_maceisa_interrupt = { | 340 | static struct irq_chip ip32_maceisa_level_interrupt = { |
341 | .name = "IP32 MACE ISA", | ||
342 | .ack = disable_maceisa_irq, | ||
343 | .mask = disable_maceisa_irq, | ||
344 | .mask_ack = disable_maceisa_irq, | ||
345 | .unmask = enable_maceisa_irq, | ||
346 | .end = end_maceisa_irq, | ||
347 | }; | ||
348 | |||
349 | static struct irq_chip ip32_maceisa_edge_interrupt = { | ||
346 | .name = "IP32 MACE ISA", | 350 | .name = "IP32 MACE ISA", |
347 | .ack = mask_and_ack_maceisa_irq, | 351 | .ack = mask_and_ack_maceisa_irq, |
348 | .mask = disable_maceisa_irq, | 352 | .mask = disable_maceisa_irq, |
@@ -498,27 +502,50 @@ void __init arch_init_irq(void) | |||
498 | for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { | 502 | for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { |
499 | switch (irq) { | 503 | switch (irq) { |
500 | case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: | 504 | case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: |
501 | set_irq_chip(irq, &ip32_mace_interrupt); | 505 | set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, |
506 | handle_level_irq, "level"); | ||
502 | break; | 507 | break; |
508 | |||
503 | case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: | 509 | case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: |
504 | set_irq_chip(irq, &ip32_macepci_interrupt); | 510 | set_irq_chip_and_handler_name(irq, |
511 | &ip32_macepci_interrupt, handle_level_irq, | ||
512 | "level"); | ||
505 | break; | 513 | break; |
514 | |||
506 | case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: | 515 | case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: |
507 | set_irq_chip(irq, &crime_edge_interrupt); | 516 | set_irq_chip_and_handler_name(irq, |
517 | &crime_edge_interrupt, handle_edge_irq, "edge"); | ||
508 | break; | 518 | break; |
509 | case CRIME_CPUERR_IRQ: | 519 | case CRIME_CPUERR_IRQ: |
510 | case CRIME_MEMERR_IRQ: | 520 | case CRIME_MEMERR_IRQ: |
511 | set_irq_chip(irq, &crime_level_interrupt); | 521 | set_irq_chip_and_handler_name(irq, |
522 | &crime_level_interrupt, handle_level_irq, | ||
523 | "level"); | ||
512 | break; | 524 | break; |
525 | |||
513 | case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: | 526 | case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: |
514 | case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: | 527 | case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: |
515 | set_irq_chip(irq, &crime_edge_interrupt); | 528 | set_irq_chip_and_handler_name(irq, |
529 | &crime_edge_interrupt, handle_edge_irq, "edge"); | ||
516 | break; | 530 | break; |
531 | |||
517 | case CRIME_VICE_IRQ: | 532 | case CRIME_VICE_IRQ: |
518 | set_irq_chip(irq, &crime_edge_interrupt); | 533 | set_irq_chip_and_handler_name(irq, |
534 | &crime_edge_interrupt, handle_edge_irq, "edge"); | ||
535 | break; | ||
536 | |||
537 | case MACEISA_PARALLEL_IRQ: | ||
538 | case MACEISA_SERIAL1_TDMAPR_IRQ: | ||
539 | case MACEISA_SERIAL2_TDMAPR_IRQ: | ||
540 | set_irq_chip_and_handler_name(irq, | ||
541 | &ip32_maceisa_edge_interrupt, handle_edge_irq, | ||
542 | "edge"); | ||
519 | break; | 543 | break; |
544 | |||
520 | default: | 545 | default: |
521 | set_irq_chip(irq, &ip32_maceisa_interrupt); | 546 | set_irq_chip_and_handler_name(irq, |
547 | &ip32_maceisa_level_interrupt, handle_level_irq, | ||
548 | "level"); | ||
522 | break; | 549 | break; |
523 | } | 550 | } |
524 | } | 551 | } |