1 files changed, 22 insertions, 22 deletions

diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c
index 75ada8a9713b..7cec0a4e527d 100644
--- a/arch/mips/sgi-ip22/ip22-mc.c
+++ b/arch/mips/sgi-ip22/ip22-mc.c
@@ -121,22 +121,22 @@ void __init sgimc_init(void)
          */
 
         /* Step 0: Make sure we turn off the watchdog in case it's
-         *         still running (which might be the case after a
-         *         soft reboot).
+         *         still running (which might be the case after a
+         *         soft reboot).
          */
         tmp = sgimc->cpuctrl0;
         tmp &= ~SGIMC_CCTRL0_WDOG;
         sgimc->cpuctrl0 = tmp;
 
         /* Step 1: The CPU/GIO error status registers will not latch
-         *         up a new error status until the register has been
-         *         cleared by the cpu.  These status registers are
-         *         cleared by writing any value to them.
+         *         up a new error status until the register has been
+         *         cleared by the cpu.  These status registers are
+         *         cleared by writing any value to them.
          */
         sgimc->cstat = sgimc->gstat = 0;
 
         /* Step 2: Enable all parity checking in cpu control register
-         *         zero.
+         *         zero.
          */
         /* don't touch parity settings for IP28 */
         tmp = sgimc->cpuctrl0;
@@ -147,7 +147,7 @@ void __init sgimc_init(void)
         sgimc->cpuctrl0 = tmp;
 
         /* Step 3: Setup the MC write buffer depth, this is controlled
-         *         in cpu control register 1 in the lower 4 bits.
+         *         in cpu control register 1 in the lower 4 bits.
          */
         tmp = sgimc->cpuctrl1;
         tmp &= ~0xf;
@@ -155,26 +155,26 @@ void __init sgimc_init(void)
         sgimc->cpuctrl1 = tmp;
 
         /* Step 4: Initialize the RPSS divider register to run as fast
-         *         as it can correctly operate.  The register is laid
-         *         out as follows:
+         *         as it can correctly operate.  The register is laid
+         *         out as follows:
          *
-         *         ----------------------------------------
-         *         |  RESERVED  |   INCREMENT   | DIVIDER |
-         *         ----------------------------------------
-         *          31        16 15            8 7       0
+         *         ----------------------------------------
+         *         |  RESERVED  |   INCREMENT   | DIVIDER |
+         *         ----------------------------------------
+         *          31        16 15            8 7       0
          *
-         *         DIVIDER determines how often a 'tick' happens,
-         *         INCREMENT determines by how the RPSS increment
-         *         registers value increases at each 'tick'. Thus,
-         *         for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
+         *         DIVIDER determines how often a 'tick' happens,
+         *         INCREMENT determines by how the RPSS increment
+         *         registers value increases at each 'tick'. Thus,
+         *         for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
          */
         sgimc->divider = 0x101;
 
         /* Step 5: Initialize GIO64 arbitrator configuration register.
          *
          * NOTE: HPC init code in sgihpc_init() must run before us because
-         *       we need to know Guiness vs. FullHouse and the board
-         *       revision on this machine. You have been warned.
+         *       we need to know Guiness vs. FullHouse and the board
+         *       revision on this machine. You have been warned.
          */
 
         /* First the basic invariants across all GIO64 implementations. */
@@ -187,18 +187,18 @@ void __init sgimc_init(void)
                 if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
                         tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC at 64bits */
                         tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp0 pipelines */
-                        tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
+                        tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
                         tmp |= SGIMC_GIOPAR_RTIMEEXP0;  /* exp0 is realtime */
                 } else {
                         tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC 64bits */
                         tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp[01] pipelined */
                         tmp |= SGIMC_GIOPAR_PLINEEXP1;
-                        tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
+                        tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
                 }
         } else {
                 /* Guiness specific settings. */
                 tmp |= SGIMC_GIOPAR_EISA64;     /* MC talks to EISA at 64bits */
-                tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
+                tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
         }
         sgimc->giopar = tmp;    /* poof */