diff options
Diffstat (limited to 'arch/mips/rb532/devices.c')
-rw-r--r-- | arch/mips/rb532/devices.c | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 44fb0a62877f..82ab395efa33 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c | |||
@@ -49,8 +49,6 @@ | |||
49 | #define GPIO_ALE (1 << 0x0a) | 49 | #define GPIO_ALE (1 << 0x0a) |
50 | #define GPIO_CLE (1 << 0x0b) | 50 | #define GPIO_CLE (1 << 0x0b) |
51 | 51 | ||
52 | extern char *board_type; | ||
53 | |||
54 | static struct resource korina_dev0_res[] = { | 52 | static struct resource korina_dev0_res[] = { |
55 | { | 53 | { |
56 | .name = "korina_regs", | 54 | .name = "korina_regs", |
@@ -265,14 +263,6 @@ static void __init parse_mac_addr(char *macstr) | |||
265 | } | 263 | } |
266 | 264 | ||
267 | 265 | ||
268 | /* DEVICE CONTROLLER 1 */ | ||
269 | #define CFG_DC_DEV1 ((void *)0xb8010010) | ||
270 | #define CFG_DC_DEV2 ((void *)0xb8010020) | ||
271 | #define CFG_DC_DEVBASE 0x0 | ||
272 | #define CFG_DC_DEVMASK 0x4 | ||
273 | #define CFG_DC_DEVC 0x8 | ||
274 | #define CFG_DC_DEVTC 0xC | ||
275 | |||
276 | /* NAND definitions */ | 266 | /* NAND definitions */ |
277 | #define NAND_CHIP_DELAY 25 | 267 | #define NAND_CHIP_DELAY 25 |
278 | 268 | ||
@@ -301,16 +291,16 @@ static void __init rb532_nand_setup(void) | |||
301 | static int __init plat_setup_devices(void) | 291 | static int __init plat_setup_devices(void) |
302 | { | 292 | { |
303 | /* Look for the CF card reader */ | 293 | /* Look for the CF card reader */ |
304 | if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK)) | 294 | if (!readl(IDT434_REG_BASE + DEV1MASK)) |
305 | rb532_devs[1] = NULL; | 295 | rb532_devs[1] = NULL; |
306 | else { | 296 | else { |
307 | cf_slot0_res[0].start = | 297 | cf_slot0_res[0].start = |
308 | readl(CFG_DC_DEV1 + CFG_DC_DEVBASE); | 298 | readl(IDT434_REG_BASE + DEV1BASE); |
309 | cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; | 299 | cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; |
310 | } | 300 | } |
311 | 301 | ||
312 | /* Read the NAND resources from the device controller */ | 302 | /* Read the NAND resources from the device controller */ |
313 | nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE); | 303 | nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE); |
314 | nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; | 304 | nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; |
315 | 305 | ||
316 | /* Initialise the NAND device */ | 306 | /* Initialise the NAND device */ |