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-rw-r--r--arch/mips/ralink/rt305x.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index 0a4bbdcf59d9..5d49a54ba8fa 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
124void __init ralink_clk_init(void) 124void __init ralink_clk_init(void)
125{ 125{
126 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; 126 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
127 unsigned long wmac_rate = 40000000;
128
127 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 129 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
128 130
129 if (soc_is_rt305x() || soc_is_rt3350()) { 131 if (soc_is_rt305x() || soc_is_rt3350()) {
@@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
176 BUG(); 178 BUG();
177 } 179 }
178 180
181 if (soc_is_rt3352() || soc_is_rt5350()) {
182 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
183
184 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
185 wmac_rate = 20000000;
186 }
187
179 ralink_clk_add("cpu", cpu_rate); 188 ralink_clk_add("cpu", cpu_rate);
180 ralink_clk_add("10000b00.spi", sys_rate); 189 ralink_clk_add("10000b00.spi", sys_rate);
181 ralink_clk_add("10000100.timer", wdt_rate); 190 ralink_clk_add("10000100.timer", wdt_rate);
191 ralink_clk_add("10000120.watchdog", wdt_rate);
182 ralink_clk_add("10000500.uart", uart_rate); 192 ralink_clk_add("10000500.uart", uart_rate);
183 ralink_clk_add("10000c00.uartlite", uart_rate); 193 ralink_clk_add("10000c00.uartlite", uart_rate);
194 ralink_clk_add("10100000.ethernet", sys_rate);
195 ralink_clk_add("10180000.wmac", wmac_rate);
184} 196}
185 197
186void __init ralink_of_remap(void) 198void __init ralink_of_remap(void)