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Diffstat (limited to 'arch/mips/ralink/mt7620.c')
-rw-r--r--arch/mips/ralink/mt7620.c465
1 files changed, 312 insertions, 153 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index a3ad56c2372d..2ea5ff6dc22e 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -17,124 +17,214 @@
17#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h> 18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/mt7620.h> 19#include <asm/mach-ralink/mt7620.h>
20#include <asm/mach-ralink/pinmux.h>
20 21
21#include "common.h" 22#include "common.h"
22 23
24/* analog */
25#define PMU0_CFG 0x88
26#define PMU_SW_SET BIT(28)
27#define A_DCDC_EN BIT(24)
28#define A_SSC_PERI BIT(19)
29#define A_SSC_GEN BIT(18)
30#define A_SSC_M 0x3
31#define A_SSC_S 16
32#define A_DLY_M 0x7
33#define A_DLY_S 8
34#define A_VTUNE_M 0xff
35
36/* digital */
37#define PMU1_CFG 0x8C
38#define DIG_SW_SEL BIT(25)
39
40/* is this a MT7620 or a MT7628 */
41enum mt762x_soc_type mt762x_soc;
42
23/* does the board have sdram or ddram */ 43/* does the board have sdram or ddram */
24static int dram_type; 44static int dram_type;
25 45
26static struct ralink_pinmux_grp mode_mux[] = { 46static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
27 { 47static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
28 .name = "i2c", 48static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
29 .mask = MT7620_GPIO_MODE_I2C, 49static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
30 .gpio_first = 1, 50static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
31 .gpio_last = 2, 51static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
32 }, { 52static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
33 .name = "spi", 53static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
34 .mask = MT7620_GPIO_MODE_SPI, 54static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
35 .gpio_first = 3, 55static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
36 .gpio_last = 6, 56static struct rt2880_pmx_func uartf_grp[] = {
37 }, { 57 FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
38 .name = "uartlite", 58 FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
39 .mask = MT7620_GPIO_MODE_UART1, 59 FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
40 .gpio_first = 15, 60 FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
41 .gpio_last = 16, 61 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
42 }, { 62 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
43 .name = "wdt", 63 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
44 .mask = MT7620_GPIO_MODE_WDT, 64};
45 .gpio_first = 17, 65static struct rt2880_pmx_func wdt_grp[] = {
46 .gpio_last = 17, 66 FUNC("wdt rst", 0, 17, 1),
47 }, { 67 FUNC("wdt refclk", 0, 17, 1),
48 .name = "mdio", 68 };
49 .mask = MT7620_GPIO_MODE_MDIO, 69static struct rt2880_pmx_func pcie_rst_grp[] = {
50 .gpio_first = 22, 70 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
51 .gpio_last = 23, 71 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
52 }, { 72};
53 .name = "rgmii1", 73static struct rt2880_pmx_func nd_sd_grp[] = {
54 .mask = MT7620_GPIO_MODE_RGMII1, 74 FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
55 .gpio_first = 24, 75 FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
56 .gpio_last = 35, 76};
57 }, { 77
58 .name = "spi refclk", 78static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
59 .mask = MT7620_GPIO_MODE_SPI_REF_CLK, 79 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
60 .gpio_first = 37, 80 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
61 .gpio_last = 39, 81 MT7620_GPIO_MODE_UART0_SHIFT),
62 }, { 82 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
63 .name = "jtag", 83 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
64 .mask = MT7620_GPIO_MODE_JTAG, 84 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
65 .gpio_first = 40, 85 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
66 .gpio_last = 44, 86 GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
67 }, { 87 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
68 /* shared lines with jtag */ 88 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
69 .name = "ephy", 89 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
70 .mask = MT7620_GPIO_MODE_EPHY, 90 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
71 .gpio_first = 40, 91 GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
72 .gpio_last = 44, 92 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
73 }, { 93 GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
74 .name = "nand", 94 GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
75 .mask = MT7620_GPIO_MODE_JTAG, 95 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
76 .gpio_first = 45, 96 GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
77 .gpio_last = 59, 97 { 0 }
78 }, { 98};
79 .name = "rgmii2", 99
80 .mask = MT7620_GPIO_MODE_RGMII2, 100static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
81 .gpio_first = 60, 101 FUNC("sdcx", 3, 19, 1),
82 .gpio_last = 71, 102 FUNC("utif", 2, 19, 1),
83 }, { 103 FUNC("gpio", 1, 19, 1),
84 .name = "wled", 104 FUNC("pwm", 0, 19, 1),
85 .mask = MT7620_GPIO_MODE_WLED, 105};
86 .gpio_first = 72, 106
87 .gpio_last = 72, 107static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
88 }, {0} 108 FUNC("sdcx", 3, 18, 1),
109 FUNC("utif", 2, 18, 1),
110 FUNC("gpio", 1, 18, 1),
111 FUNC("pwm", 0, 18, 1),
112};
113
114static struct rt2880_pmx_func uart2_grp_mt7628[] = {
115 FUNC("sdcx", 3, 20, 2),
116 FUNC("pwm", 2, 20, 2),
117 FUNC("gpio", 1, 20, 2),
118 FUNC("uart", 0, 20, 2),
119};
120
121static struct rt2880_pmx_func uart1_grp_mt7628[] = {
122 FUNC("sdcx", 3, 45, 2),
123 FUNC("pwm", 2, 45, 2),
124 FUNC("gpio", 1, 45, 2),
125 FUNC("uart", 0, 45, 2),
126};
127
128static struct rt2880_pmx_func i2c_grp_mt7628[] = {
129 FUNC("-", 3, 4, 2),
130 FUNC("debug", 2, 4, 2),
131 FUNC("gpio", 1, 4, 2),
132 FUNC("i2c", 0, 4, 2),
133};
134
135static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
136static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
137static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
138static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
139
140static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
141 FUNC("jtag", 3, 22, 8),
142 FUNC("utif", 2, 22, 8),
143 FUNC("gpio", 1, 22, 8),
144 FUNC("sdcx", 0, 22, 8),
145};
146
147static struct rt2880_pmx_func uart0_grp_mt7628[] = {
148 FUNC("-", 3, 12, 2),
149 FUNC("-", 2, 12, 2),
150 FUNC("gpio", 1, 12, 2),
151 FUNC("uart", 0, 12, 2),
152};
153
154static struct rt2880_pmx_func i2s_grp_mt7628[] = {
155 FUNC("antenna", 3, 0, 4),
156 FUNC("pcm", 2, 0, 4),
157 FUNC("gpio", 1, 0, 4),
158 FUNC("i2s", 0, 0, 4),
159};
160
161static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
162 FUNC("-", 3, 6, 1),
163 FUNC("refclk", 2, 6, 1),
164 FUNC("gpio", 1, 6, 1),
165 FUNC("spi", 0, 6, 1),
166};
167
168static struct rt2880_pmx_func spis_grp_mt7628[] = {
169 FUNC("pwm", 3, 14, 4),
170 FUNC("util", 2, 14, 4),
171 FUNC("gpio", 1, 14, 4),
172 FUNC("spis", 0, 14, 4),
89}; 173};
90 174
91static struct ralink_pinmux_grp uart_mux[] = { 175static struct rt2880_pmx_func gpio_grp_mt7628[] = {
92 { 176 FUNC("pcie", 3, 11, 1),
93 .name = "uartf", 177 FUNC("refclk", 2, 11, 1),
94 .mask = MT7620_GPIO_MODE_UARTF, 178 FUNC("gpio", 1, 11, 1),
95 .gpio_first = 7, 179 FUNC("gpio", 0, 11, 1),
96 .gpio_last = 14,
97 }, {
98 .name = "pcm uartf",
99 .mask = MT7620_GPIO_MODE_PCM_UARTF,
100 .gpio_first = 7,
101 .gpio_last = 14,
102 }, {
103 .name = "pcm i2s",
104 .mask = MT7620_GPIO_MODE_PCM_I2S,
105 .gpio_first = 7,
106 .gpio_last = 14,
107 }, {
108 .name = "i2s uartf",
109 .mask = MT7620_GPIO_MODE_I2S_UARTF,
110 .gpio_first = 7,
111 .gpio_last = 14,
112 }, {
113 .name = "pcm gpio",
114 .mask = MT7620_GPIO_MODE_PCM_GPIO,
115 .gpio_first = 11,
116 .gpio_last = 14,
117 }, {
118 .name = "gpio uartf",
119 .mask = MT7620_GPIO_MODE_GPIO_UARTF,
120 .gpio_first = 7,
121 .gpio_last = 10,
122 }, {
123 .name = "gpio i2s",
124 .mask = MT7620_GPIO_MODE_GPIO_I2S,
125 .gpio_first = 7,
126 .gpio_last = 10,
127 }, {
128 .name = "gpio",
129 .mask = MT7620_GPIO_MODE_GPIO,
130 }, {0}
131}; 180};
132 181
133struct ralink_pinmux rt_gpio_pinmux = { 182#define MT7628_GPIO_MODE_MASK 0x3
134 .mode = mode_mux, 183
135 .uart = uart_mux, 184#define MT7628_GPIO_MODE_PWM1 30
136 .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT, 185#define MT7628_GPIO_MODE_PWM0 28
137 .uart_mask = MT7620_GPIO_MODE_UART0_MASK, 186#define MT7628_GPIO_MODE_UART2 26
187#define MT7628_GPIO_MODE_UART1 24
188#define MT7628_GPIO_MODE_I2C 20
189#define MT7628_GPIO_MODE_REFCLK 18
190#define MT7628_GPIO_MODE_PERST 16
191#define MT7628_GPIO_MODE_WDT 14
192#define MT7628_GPIO_MODE_SPI 12
193#define MT7628_GPIO_MODE_SDMODE 10
194#define MT7628_GPIO_MODE_UART0 8
195#define MT7628_GPIO_MODE_I2S 6
196#define MT7628_GPIO_MODE_CS1 4
197#define MT7628_GPIO_MODE_SPIS 2
198#define MT7628_GPIO_MODE_GPIO 0
199
200static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
201 GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
202 1, MT7628_GPIO_MODE_PWM1),
203 GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
204 1, MT7628_GPIO_MODE_PWM0),
205 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
206 1, MT7628_GPIO_MODE_UART2),
207 GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
208 1, MT7628_GPIO_MODE_UART1),
209 GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
210 1, MT7628_GPIO_MODE_I2C),
211 GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
212 GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
213 GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
214 GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
215 GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
216 1, MT7628_GPIO_MODE_SDMODE),
217 GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
218 1, MT7628_GPIO_MODE_UART0),
219 GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
220 1, MT7628_GPIO_MODE_I2S),
221 GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
222 1, MT7628_GPIO_MODE_CS1),
223 GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
224 1, MT7628_GPIO_MODE_SPIS),
225 GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
226 1, MT7628_GPIO_MODE_GPIO),
227 { 0 }
138}; 228};
139 229
140static __init u32 230static __init u32
@@ -287,29 +377,42 @@ void __init ralink_clk_init(void)
287 377
288 xtal_rate = mt7620_get_xtal_rate(); 378 xtal_rate = mt7620_get_xtal_rate();
289 379
290 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
291 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
292
293 cpu_rate = mt7620_get_cpu_rate(pll_rate);
294 dram_rate = mt7620_get_dram_rate(pll_rate);
295 sys_rate = mt7620_get_sys_rate(cpu_rate);
296 periph_rate = mt7620_get_periph_rate(xtal_rate);
297
298#define RFMT(label) label ":%lu.%03luMHz " 380#define RFMT(label) label ":%lu.%03luMHz "
299#define RINT(x) ((x) / 1000000) 381#define RINT(x) ((x) / 1000000)
300#define RFRAC(x) (((x) / 1000) % 1000) 382#define RFRAC(x) (((x) / 1000) % 1000)
301 383
302 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), 384 if (mt762x_soc == MT762X_SOC_MT7628AN) {
303 RINT(xtal_rate), RFRAC(xtal_rate), 385 if (xtal_rate == MHZ(40))
304 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), 386 cpu_rate = MHZ(580);
305 RINT(pll_rate), RFRAC(pll_rate)); 387 else
388 cpu_rate = MHZ(575);
389 dram_rate = sys_rate = cpu_rate / 3;
390 periph_rate = MHZ(40);
391
392 ralink_clk_add("10000d00.uartlite", periph_rate);
393 ralink_clk_add("10000e00.uartlite", periph_rate);
394 } else {
395 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
396 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
397
398 cpu_rate = mt7620_get_cpu_rate(pll_rate);
399 dram_rate = mt7620_get_dram_rate(pll_rate);
400 sys_rate = mt7620_get_sys_rate(cpu_rate);
401 periph_rate = mt7620_get_periph_rate(xtal_rate);
402
403 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
404 RINT(xtal_rate), RFRAC(xtal_rate),
405 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
406 RINT(pll_rate), RFRAC(pll_rate));
407
408 ralink_clk_add("10000500.uart", periph_rate);
409 }
306 410
307 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), 411 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
308 RINT(cpu_rate), RFRAC(cpu_rate), 412 RINT(cpu_rate), RFRAC(cpu_rate),
309 RINT(dram_rate), RFRAC(dram_rate), 413 RINT(dram_rate), RFRAC(dram_rate),
310 RINT(sys_rate), RFRAC(sys_rate), 414 RINT(sys_rate), RFRAC(sys_rate),
311 RINT(periph_rate), RFRAC(periph_rate)); 415 RINT(periph_rate), RFRAC(periph_rate));
312
313#undef RFRAC 416#undef RFRAC
314#undef RINT 417#undef RINT
315#undef RFMT 418#undef RFMT
@@ -317,9 +420,9 @@ void __init ralink_clk_init(void)
317 ralink_clk_add("cpu", cpu_rate); 420 ralink_clk_add("cpu", cpu_rate);
318 ralink_clk_add("10000100.timer", periph_rate); 421 ralink_clk_add("10000100.timer", periph_rate);
319 ralink_clk_add("10000120.watchdog", periph_rate); 422 ralink_clk_add("10000120.watchdog", periph_rate);
320 ralink_clk_add("10000500.uart", periph_rate);
321 ralink_clk_add("10000b00.spi", sys_rate); 423 ralink_clk_add("10000b00.spi", sys_rate);
322 ralink_clk_add("10000c00.uartlite", periph_rate); 424 ralink_clk_add("10000c00.uartlite", periph_rate);
425 ralink_clk_add("10180000.wmac", xtal_rate);
323} 426}
324 427
325void __init ralink_of_remap(void) 428void __init ralink_of_remap(void)
@@ -331,6 +434,52 @@ void __init ralink_of_remap(void)
331 panic("Failed to remap core resources"); 434 panic("Failed to remap core resources");
332} 435}
333 436
437static __init void
438mt7620_dram_init(struct ralink_soc_info *soc_info)
439{
440 switch (dram_type) {
441 case SYSCFG0_DRAM_TYPE_SDRAM:
442 pr_info("Board has SDRAM\n");
443 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
444 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
445 break;
446
447 case SYSCFG0_DRAM_TYPE_DDR1:
448 pr_info("Board has DDR1\n");
449 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
450 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
451 break;
452
453 case SYSCFG0_DRAM_TYPE_DDR2:
454 pr_info("Board has DDR2\n");
455 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
456 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
457 break;
458 default:
459 BUG();
460 }
461}
462
463static __init void
464mt7628_dram_init(struct ralink_soc_info *soc_info)
465{
466 switch (dram_type) {
467 case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
468 pr_info("Board has DDR1\n");
469 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
470 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
471 break;
472
473 case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
474 pr_info("Board has DDR2\n");
475 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
476 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
477 break;
478 default:
479 BUG();
480 }
481}
482
334void prom_soc_init(struct ralink_soc_info *soc_info) 483void prom_soc_init(struct ralink_soc_info *soc_info)
335{ 484{
336 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); 485 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
@@ -339,22 +488,36 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
339 u32 n1; 488 u32 n1;
340 u32 rev; 489 u32 rev;
341 u32 cfg0; 490 u32 cfg0;
491 u32 pmu0;
492 u32 pmu1;
493 u32 bga;
342 494
343 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 495 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
344 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 496 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
345 497 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
346 if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) { 498 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
347 name = "MT7620N"; 499
348 soc_info->compatible = "ralink,mt7620n-soc"; 500 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
349 } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) { 501 if (bga) {
350 name = "MT7620A"; 502 mt762x_soc = MT762X_SOC_MT7620A;
351 soc_info->compatible = "ralink,mt7620a-soc"; 503 name = "MT7620A";
504 soc_info->compatible = "ralink,mt7620a-soc";
505 } else {
506 mt762x_soc = MT762X_SOC_MT7620N;
507 name = "MT7620N";
508 soc_info->compatible = "ralink,mt7620n-soc";
509#ifdef CONFIG_PCI
510 panic("mt7620n is only supported for non pci kernels");
511#endif
512 }
513 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
514 mt762x_soc = MT762X_SOC_MT7628AN;
515 name = "MT7628AN";
516 soc_info->compatible = "ralink,mt7628an-soc";
352 } else { 517 } else {
353 panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1); 518 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
354 } 519 }
355 520
356 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
357
358 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 521 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
359 "Ralink %s ver:%u eco:%u", 522 "Ralink %s ver:%u eco:%u",
360 name, 523 name,
@@ -364,26 +527,22 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
364 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); 527 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
365 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; 528 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
366 529
367 switch (dram_type) {
368 case SYSCFG0_DRAM_TYPE_SDRAM:
369 pr_info("Board has SDRAM\n");
370 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
371 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
372 break;
373
374 case SYSCFG0_DRAM_TYPE_DDR1:
375 pr_info("Board has DDR1\n");
376 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
377 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
378 break;
379
380 case SYSCFG0_DRAM_TYPE_DDR2:
381 pr_info("Board has DDR2\n");
382 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
383 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
384 break;
385 default:
386 BUG();
387 }
388 soc_info->mem_base = MT7620_DRAM_BASE; 530 soc_info->mem_base = MT7620_DRAM_BASE;
531 if (mt762x_soc == MT762X_SOC_MT7628AN)
532 mt7628_dram_init(soc_info);
533 else
534 mt7620_dram_init(soc_info);
535
536 pmu0 = __raw_readl(sysc + PMU0_CFG);
537 pmu1 = __raw_readl(sysc + PMU1_CFG);
538
539 pr_info("Analog PMU set to %s control\n",
540 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
541 pr_info("Digital PMU set to %s control\n",
542 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
543
544 if (mt762x_soc == MT762X_SOC_MT7628AN)
545 rt2880_pinmux_data = mt7628an_pinmux_data;
546 else
547 rt2880_pinmux_data = mt7620a_pinmux_data;
389} 548}
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 13:57:45 -0400