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Diffstat (limited to 'arch/mips/ralink/irq.c')
-rw-r--r--arch/mips/ralink/irq.c45
1 files changed, 33 insertions, 12 deletions
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
index 781b3d14a489..7cf91b92e9d1 100644
--- a/arch/mips/ralink/irq.c
+++ b/arch/mips/ralink/irq.c
@@ -20,14 +20,6 @@
20 20
21#include "common.h" 21#include "common.h"
22 22
23/* INTC register offsets */
24#define INTC_REG_STATUS0 0x00
25#define INTC_REG_STATUS1 0x04
26#define INTC_REG_TYPE 0x20
27#define INTC_REG_RAW_STATUS 0x30
28#define INTC_REG_ENABLE 0x34
29#define INTC_REG_DISABLE 0x38
30
31#define INTC_INT_GLOBAL BIT(31) 23#define INTC_INT_GLOBAL BIT(31)
32 24
33#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2) 25#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
@@ -44,16 +36,36 @@
44 36
45#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9) 37#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
46 38
39enum rt_intc_regs_enum {
40 INTC_REG_STATUS0 = 0,
41 INTC_REG_STATUS1,
42 INTC_REG_TYPE,
43 INTC_REG_RAW_STATUS,
44 INTC_REG_ENABLE,
45 INTC_REG_DISABLE,
46};
47
48static u32 rt_intc_regs[] = {
49 [INTC_REG_STATUS0] = 0x00,
50 [INTC_REG_STATUS1] = 0x04,
51 [INTC_REG_TYPE] = 0x20,
52 [INTC_REG_RAW_STATUS] = 0x30,
53 [INTC_REG_ENABLE] = 0x34,
54 [INTC_REG_DISABLE] = 0x38,
55};
56
47static void __iomem *rt_intc_membase; 57static void __iomem *rt_intc_membase;
48 58
59static int rt_perfcount_irq;
60
49static inline void rt_intc_w32(u32 val, unsigned reg) 61static inline void rt_intc_w32(u32 val, unsigned reg)
50{ 62{
51 __raw_writel(val, rt_intc_membase + reg); 63 __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
52} 64}
53 65
54static inline u32 rt_intc_r32(unsigned reg) 66static inline u32 rt_intc_r32(unsigned reg)
55{ 67{
56 return __raw_readl(rt_intc_membase + reg); 68 return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
57} 69}
58 70
59static void ralink_intc_irq_unmask(struct irq_data *d) 71static void ralink_intc_irq_unmask(struct irq_data *d)
@@ -73,6 +85,11 @@ static struct irq_chip ralink_intc_irq_chip = {
73 .irq_mask_ack = ralink_intc_irq_mask, 85 .irq_mask_ack = ralink_intc_irq_mask,
74}; 86};
75 87
88int get_c0_perfcount_int(void)
89{
90 return rt_perfcount_irq;
91}
92
76unsigned int get_c0_compare_int(void) 93unsigned int get_c0_compare_int(void)
77{ 94{
78 return CP0_LEGACY_COMPARE_IRQ; 95 return CP0_LEGACY_COMPARE_IRQ;
@@ -134,6 +151,10 @@ static int __init intc_of_init(struct device_node *node,
134 struct irq_domain *domain; 151 struct irq_domain *domain;
135 int irq; 152 int irq;
136 153
154 if (!of_property_read_u32_array(node, "ralink,intc-registers",
155 rt_intc_regs, 6))
156 pr_info("intc: using register map from devicetree\n");
157
137 irq = irq_of_parse_and_map(node, 0); 158 irq = irq_of_parse_and_map(node, 0);
138 if (!irq) 159 if (!irq)
139 panic("Failed to get INTC IRQ"); 160 panic("Failed to get INTC IRQ");
@@ -167,13 +188,13 @@ static int __init intc_of_init(struct device_node *node,
167 irq_set_handler_data(irq, domain); 188 irq_set_handler_data(irq, domain);
168 189
169 /* tell the kernel which irq is used for performance monitoring */ 190 /* tell the kernel which irq is used for performance monitoring */
170 cp0_perfcount_irq = irq_create_mapping(domain, 9); 191 rt_perfcount_irq = irq_create_mapping(domain, 9);
171 192
172 return 0; 193 return 0;
173} 194}
174 195
175static struct of_device_id __initdata of_irq_ids[] = { 196static struct of_device_id __initdata of_irq_ids[] = {
176 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init }, 197 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
177 { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, 198 { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
178 {}, 199 {},
179}; 200};