diff options
Diffstat (limited to 'arch/mips/pmc-sierra')
-rw-r--r-- | arch/mips/pmc-sierra/msp71xx/msp_serial.c | 165 |
1 files changed, 165 insertions, 0 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c new file mode 100644 index 000000000000..c41b53faa8f6 --- /dev/null +++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c | |||
@@ -0,0 +1,165 @@ | |||
1 | /* | ||
2 | * The setup file for serial related hardware on PMC-Sierra MSP processors. | ||
3 | * | ||
4 | * Copyright 2005 PMC-Sierra, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
21 | * | ||
22 | * You should have received a copy of the GNU General Public License along | ||
23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
25 | */ | ||
26 | |||
27 | #include <linux/serial.h> | ||
28 | #include <linux/serial_core.h> | ||
29 | #include <linux/serial_reg.h> | ||
30 | |||
31 | #include <asm/bootinfo.h> | ||
32 | #include <asm/io.h> | ||
33 | #include <asm/processor.h> | ||
34 | #include <asm/serial.h> | ||
35 | |||
36 | #include <msp_prom.h> | ||
37 | #include <msp_int.h> | ||
38 | #include <msp_regs.h> | ||
39 | |||
40 | #ifdef CONFIG_KGDB | ||
41 | /* | ||
42 | * kgdb uses serial port 1 so the console can remain on port 0. | ||
43 | * To use port 0 change the definition to read as follows: | ||
44 | * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE) | ||
45 | */ | ||
46 | #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE) | ||
47 | |||
48 | int putDebugChar(char c) | ||
49 | { | ||
50 | volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE; | ||
51 | uint32_t val = (uint32_t)c; | ||
52 | |||
53 | local_irq_disable(); | ||
54 | while( !(uart[5] & 0x20) ); /* Wait for TXRDY */ | ||
55 | uart[0] = val; | ||
56 | while( !(uart[5] & 0x20) ); /* Wait for TXRDY */ | ||
57 | local_irq_enable(); | ||
58 | |||
59 | return 1; | ||
60 | } | ||
61 | |||
62 | char getDebugChar(void) | ||
63 | { | ||
64 | volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE; | ||
65 | uint32_t val; | ||
66 | |||
67 | while( !(uart[5] & 0x01) ); /* Wait for RXRDY */ | ||
68 | val = uart[0]; | ||
69 | |||
70 | return (char)val; | ||
71 | } | ||
72 | |||
73 | void initDebugPort(unsigned int uartclk, unsigned int baudrate) | ||
74 | { | ||
75 | unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate); | ||
76 | |||
77 | /* Enable FIFOs */ | ||
78 | writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | | ||
79 | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4, | ||
80 | (char *)DEBUG_PORT_BASE + (UART_FCR * 4)); | ||
81 | |||
82 | /* Select brtc divisor */ | ||
83 | writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4)); | ||
84 | |||
85 | /* Store divisor lsb */ | ||
86 | writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4)); | ||
87 | |||
88 | /* Store divisor msb */ | ||
89 | writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4)); | ||
90 | |||
91 | /* Set 8N1 mode */ | ||
92 | writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4)); | ||
93 | |||
94 | /* Disable flow control */ | ||
95 | writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4)); | ||
96 | |||
97 | /* Disable receive interrupt(!) */ | ||
98 | writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4)); | ||
99 | } | ||
100 | #endif | ||
101 | |||
102 | void __init msp_serial_setup(void) | ||
103 | { | ||
104 | char *s; | ||
105 | char *endp; | ||
106 | struct uart_port up; | ||
107 | unsigned int uartclk; | ||
108 | |||
109 | memset(&up, 0, sizeof(up)); | ||
110 | |||
111 | /* Check if clock was specified in environment */ | ||
112 | s = prom_getenv("uartfreqhz"); | ||
113 | if(!(s && *s && (uartclk = simple_strtoul(s, &endp, 10)) && *endp == 0)) | ||
114 | uartclk = MSP_BASE_BAUD; | ||
115 | ppfinit("UART clock set to %d\n", uartclk); | ||
116 | |||
117 | /* Initialize first serial port */ | ||
118 | up.mapbase = MSP_UART0_BASE; | ||
119 | up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); | ||
120 | up.irq = MSP_INT_UART0; | ||
121 | up.uartclk = uartclk; | ||
122 | up.regshift = 2; | ||
123 | up.iotype = UPIO_DWAPB; /* UPIO_MEM like */ | ||
124 | up.flags = STD_COM_FLAGS; | ||
125 | up.type = PORT_16550A; | ||
126 | up.line = 0; | ||
127 | up.private_data = (void*)UART0_STATUS_REG; | ||
128 | if (early_serial_setup(&up)) | ||
129 | printk(KERN_ERR "Early serial init of port 0 failed\n"); | ||
130 | |||
131 | /* Initialize the second serial port, if one exists */ | ||
132 | switch (mips_machtype) { | ||
133 | case MACH_MSP4200_EVAL: | ||
134 | case MACH_MSP4200_GW: | ||
135 | case MACH_MSP4200_FPGA: | ||
136 | case MACH_MSP7120_EVAL: | ||
137 | case MACH_MSP7120_GW: | ||
138 | case MACH_MSP7120_FPGA: | ||
139 | /* Enable UART1 on MSP4200 and MSP7120 */ | ||
140 | *GPIO_CFG2_REG = 0x00002299; | ||
141 | |||
142 | #ifdef CONFIG_KGDB | ||
143 | /* Initialize UART1 for kgdb since PMON doesn't */ | ||
144 | if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) { | ||
145 | if( mips_machtype == MACH_MSP4200_FPGA | ||
146 | || mips_machtype == MACH_MSP7120_FPGA ) | ||
147 | initDebugPort(uartclk,19200); | ||
148 | else | ||
149 | initDebugPort(uartclk,57600); | ||
150 | } | ||
151 | #endif | ||
152 | break; | ||
153 | |||
154 | default: | ||
155 | return; /* No second serial port, good-bye. */ | ||
156 | } | ||
157 | |||
158 | up.mapbase = MSP_UART1_BASE; | ||
159 | up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); | ||
160 | up.irq = MSP_INT_UART1; | ||
161 | up.line = 1; | ||
162 | up.private_data = (void*)UART1_STATUS_REG; | ||
163 | if (early_serial_setup(&up)) | ||
164 | printk(KERN_ERR "Early serial init of port 1 failed\n"); | ||
165 | } | ||