3 files changed, 89 insertions, 163 deletions

diff --git a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h b/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h
deleted file mode 100644
index 31c5523276fa..000000000000
--- a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- *  arch/mips/pmc-sierra/yosemite/i2c-yosemite.h
- *
- *  Copyright (C) 2003 PMC-Sierra Inc.
- *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __I2C_YOSEMITE_H
-#define __I2C_YOSEMITE_H
-
-/* Read and Write operations to the chip */
-
-#define TITAN_I2C_BASE                  0xbb000000      /* XXX Needs to change */
-
-#define TITAN_I2C_WRITE(offset, data)   \
-                                        *(volatile unsigned long *)(TITAN_I2C_BASE + offset) = data
-
-#define TITAN_I2C_READ(offset) *(volatile unsigned long *)(TITAN_I2C_BASE + offset)
-
-
-/* Local constansts*/
-#define TITAN_I2C_MAX_FILTER            15
-#define TITAN_I2C_MAX_CLK               1023
-#define TITAN_I2C_MAX_ARBF              15
-#define TITAN_I2C_MAX_NAK               15
-#define TITAN_I2C_MAX_MASTERCODE        7
-#define TITAN_I2C_MAX_WORDS_PER_RW      4
-#define TITAN_I2C_MAX_POLL              100
-
-/* Registers used for I2C work */
-#define TITAN_I2C_SCMB_CONTROL          0x0180  /* SCMB Control */
-#define TITAN_I2C_SCMB_CLOCK_A          0x0184  /* SCMB Clock A */
-#define TITAN_I2C_SCMB_CLOCK_B          0x0188  /* SCMB Clock B */
-#define TITAN_I2C_CONFIG                0x01A0  /* I2C Config */
-#define TITAN_I2C_COMMAND               0x01A4  /* I2C Command */
-#define TITAN_I2C_SLAVE_ADDRESS         0x01A8  /* I2C Slave Address */
-#define TITAN_I2C_DATA                  0x01AC  /* I2C Data [15:0] */
-#define TITAN_I2C_INTERRUPTS            0x01BC  /* I2C Interrupts */
-
-/* Error */
-#define TITAN_I2C_ERR_ARB_LOST          (-9220)
-#define TITAN_I2C_ERR_NO_RESP           (-9221)
-#define TITAN_I2C_ERR_DATA_COLLISION    (-9222)
-#define TITAN_I2C_ERR_TIMEOUT           (-9223)
-#define TITAN_I2C_ERR_OK                0
-
-/* I2C Command Type */
-typedef enum {
-        TITAN_I2C_CMD_WRITE = 0,
-        TITAN_I2C_CMD_READ = 1,
-        TITAN_I2C_CMD_READ_WRITE = 2
-} titan_i2c_cmd_type;
-
-/* I2C structures */
-typedef struct {
-        int filtera;            /* Register 0x0184, bits 15 - 12 */
-        int clka;               /* Register 0x0184, bits 9 - 0 */
-        int filterb;            /* Register 0x0188, bits 15 - 12 */
-        int clkb;               /* Register 0x0188, bits 9 - 0 */
-} titan_i2c_config;
-
-/* I2C command type */
-typedef struct {
-        titan_i2c_cmd_type type;        /* Type of command */
-        int num_arb;            /* Register 0x01a0, bits 15 - 12 */
-        int num_nak;            /* Register 0x01a0, bits 11 - 8 */
-        int addr_size;          /* Register 0x01a0, bit 7 */
-        int mst_code;           /* Register 0x01a0, bits 6 - 4 */
-        int arb_en;             /* Register 0x01a0, bit 1 */
-        int speed;              /* Register 0x01a0, bit 0 */
-        int slave_addr;         /* Register 0x01a8 */
-        int write_size;         /* Register 0x01a4, bits 10 - 8 */
-        unsigned int *data;     /* Register 0x01ac */
-} titan_i2c_command;
-
-#endif                          /* __I2C_YOSEMITE_H */
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
index 9b9936de6589..35dc435846a6 100644
--- a/arch/mips/pmc-sierra/yosemite/prom.c
+++ b/arch/mips/pmc-sierra/yosemite/prom.c
@@ -19,6 +19,7 @@
 #include <asm/pgtable.h>
 #include <asm/processor.h>
 #include <asm/reboot.h>
+#include <asm/smp-ops.h>
 #include <asm/system.h>
 #include <asm/bootinfo.h>
 #include <asm/pmon.h>
@@ -78,6 +79,8 @@ static void prom_halt(void)
                 __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
 }
 
+extern struct plat_smp_ops yos_smp_ops;
+
 /*
  * Init routine which accepts the variables from PMON
  */
@@ -126,9 +129,9 @@ void __init prom_init(void)
                 env++;
         }
 
-        mips_machtype = MACH_TITAN_YOSEMITE;
-
         prom_grab_secondary();
+
+        register_smp_ops(&yos_smp_ops);
 }
 
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index b0f12cd2968a..653f3ec61cab 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -42,70 +42,6 @@ void __init prom_grab_secondary(void)
                       launchstack + LAUNCHSTACK_SIZE, 0);
 }
 
-/*
- * Detect available CPUs, populate phys_cpu_present_map before smp_init
- *
- * We don't want to start the secondary CPU yet nor do we have a nice probing
- * feature in PMON so we just assume presence of the secondary core.
- */
-void __init plat_smp_setup(void)
-{
-        int i;
-
-        cpus_clear(phys_cpu_present_map);
-
-        for (i = 0; i < 2; i++) {
-                cpu_set(i, phys_cpu_present_map);
-                __cpu_number_map[i]     = i;
-                __cpu_logical_map[i]    = i;
-        }
-}
-
-void __init plat_prepare_cpus(unsigned int max_cpus)
-{
-        /*
-         * Be paranoid.  Enable the IPI only if we're really about to go SMP.
-         */
-        if (cpus_weight(cpu_possible_map))
-                set_c0_status(STATUSF_IP5);
-}
-
-/*
- * Firmware CPU startup hook
- * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
- * It launches the next * available CPU and copies some information on the
- * stack so the first thing we do is throw away that stuff and load useful
- * values into the registers ...
- */
-void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
-{
-        unsigned long gp = (unsigned long) task_thread_info(idle);
-        unsigned long sp = __KSTK_TOS(idle);
-
-        secondary_sp = sp;
-        secondary_gp = gp;
-
-        spin_unlock(&launch_lock);
-}
-
-/* Hook for after all CPUs are online */
-void prom_cpus_done(void)
-{
-}
-
-/*
- *  After we've done initial boot, this function is called to allow the
- *  board code to clean up state, if needed
- */
-void __cpuinit prom_init_secondary(void)
-{
-        set_c0_status(ST0_CO | ST0_IE | ST0_IM);
-}
-
-void __cpuinit prom_smp_finish(void)
-{
-}
-
 void titan_mailbox_irq(void)
 {
         int cpu = smp_processor_id();
@@ -133,7 +69,7 @@ void titan_mailbox_irq(void)
 /*
  * Send inter-processor interrupt
  */
-void core_send_ipi(int cpu, unsigned int action)
+static void yos_send_ipi_single(int cpu, unsigned int action)
 {
         /*
          * Generate an INTMSG so that it can be sent over to the
@@ -159,3 +95,86 @@ void core_send_ipi(int cpu, unsigned int action)
                 break;
         }
 }
+
+static void yos_send_ipi_mask(cpumask_t mask, unsigned int action)
+{
+        unsigned int i;
+
+        for_each_cpu_mask(i, mask)
+                yos_send_ipi_single(i, action);
+}
+
+/*
+ *  After we've done initial boot, this function is called to allow the
+ *  board code to clean up state, if needed
+ */
+static void __cpuinit yos_init_secondary(void)
+{
+        set_c0_status(ST0_CO | ST0_IE | ST0_IM);
+}
+
+static void __cpuinit yos_smp_finish(void)
+{
+}
+
+/* Hook for after all CPUs are online */
+static void yos_cpus_done(void)
+{
+}
+
+/*
+ * Firmware CPU startup hook
+ * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
+ * It launches the next * available CPU and copies some information on the
+ * stack so the first thing we do is throw away that stuff and load useful
+ * values into the registers ...
+ */
+static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
+{
+        unsigned long gp = (unsigned long) task_thread_info(idle);
+        unsigned long sp = __KSTK_TOS(idle);
+
+        secondary_sp = sp;
+        secondary_gp = gp;
+
+        spin_unlock(&launch_lock);
+}
+
+/*
+ * Detect available CPUs, populate phys_cpu_present_map before smp_init
+ *
+ * We don't want to start the secondary CPU yet nor do we have a nice probing
+ * feature in PMON so we just assume presence of the secondary core.
+ */
+static void __init yos_smp_setup(void)
+{
+        int i;
+
+        cpus_clear(phys_cpu_present_map);
+
+        for (i = 0; i < 2; i++) {
+                cpu_set(i, phys_cpu_present_map);
+                __cpu_number_map[i]     = i;
+                __cpu_logical_map[i]    = i;
+        }
+}
+
+static void __init yos_prepare_cpus(unsigned int max_cpus)
+{
+        /*
+         * Be paranoid.  Enable the IPI only if we're really about to go SMP.
+         */
+        if (cpus_weight(cpu_possible_map))
+                set_c0_status(STATUSF_IP5);
+}
+
+struct plat_smp_ops yos_smp_ops = {
+        .send_ipi_single        = yos_send_ipi_single,
+        .send_ipi_mask          = yos_send_ipi_mask,
+        .init_secondary         = yos_init_secondary,
+        .smp_finish             = yos_smp_finish,
+        .cpus_done              = yos_cpus_done,
+        .boot_secondary         = yos_boot_secondary,
+        .smp_setup              = yos_smp_setup,
+        .prepare_cpus           = yos_prepare_cpus,
+};