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-rw-r--r--arch/mips/pmc-sierra/yosemite/irq.c167
1 files changed, 167 insertions, 0 deletions
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
new file mode 100644
index 000000000000..f4e2897d9bf7
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1/*
2 * Copyright (C) 2003 PMC-Sierra Inc.
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Second level Interrupt handlers for the PMC-Sierra Titan/Yosemite board
26 */
27#include <linux/config.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/kernel_stat.h>
31#include <linux/module.h>
32#include <linux/signal.h>
33#include <linux/sched.h>
34#include <linux/types.h>
35#include <linux/interrupt.h>
36#include <linux/ioport.h>
37#include <linux/irq.h>
38#include <linux/timex.h>
39#include <linux/slab.h>
40#include <linux/random.h>
41#include <linux/bitops.h>
42#include <asm/bootinfo.h>
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/irq_cpu.h>
46#include <asm/mipsregs.h>
47#include <asm/system.h>
48#include <asm/titan_dep.h>
49
50/* Hypertransport specific */
51#define IRQ_ACK_BITS 0x00000000 /* Ack bits */
52
53#define HYPERTRANSPORT_INTA 0x78 /* INTA# */
54#define HYPERTRANSPORT_INTB 0x79 /* INTB# */
55#define HYPERTRANSPORT_INTC 0x7a /* INTC# */
56#define HYPERTRANSPORT_INTD 0x7b /* INTD# */
57
58extern asmlinkage void titan_handle_int(void);
59extern void jaguar_mailbox_irq(struct pt_regs *);
60
61/*
62 * Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
63 * For interprocessor interrupts, the best thing to do is to use the INTMSG
64 * register. We use the same external interrupt line, i.e. INTB3 and monitor
65 * another status bit
66 */
67asmlinkage void ll_ht_smp_irq_handler(int irq, struct pt_regs *regs)
68{
69 u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
70
71 /* Ack all the bits that correspond to the interrupt sources */
72 if (status != 0)
73 OCD_WRITE(RM9000x2_OCD_INTP0STATUS4, IRQ_ACK_BITS);
74
75 status = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
76 if (status != 0)
77 OCD_WRITE(RM9000x2_OCD_INTP1STATUS4, IRQ_ACK_BITS);
78
79#ifdef CONFIG_HT_LEVEL_TRIGGER
80 /*
81 * Level Trigger Mode only. Send the HT EOI message back to the source.
82 */
83 switch (status) {
84 case 0x1000000:
85 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
86 break;
87 case 0x2000000:
88 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
89 break;
90 case 0x4000000:
91 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
92 break;
93 case 0x8000000:
94 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
95 break;
96 case 0x0000001:
97 /* PLX */
98 OCD_WRITE(RM9000x2_OCD_HTEOI, 0x20);
99 OCD_WRITE(IRQ_CLEAR_REG, IRQ_ACK_BITS);
100 break;
101 case 0xf000000:
102 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
103 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
104 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
105 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
106 break;
107 }
108#endif /* CONFIG_HT_LEVEL_TRIGGER */
109
110 do_IRQ(irq, regs);
111}
112
113asmlinkage void do_extended_irq(struct pt_regs *regs)
114{
115 unsigned int intcontrol = read_c0_intcontrol();
116 unsigned int cause = read_c0_cause();
117 unsigned int status = read_c0_status();
118 unsigned int pending_sr, pending_ic;
119
120 pending_sr = status & cause & 0xff00;
121 pending_ic = (cause >> 8) & intcontrol & 0xff00;
122
123 if (pending_ic & (1 << 13))
124 do_IRQ(13, regs);
125
126}
127
128#ifdef CONFIG_KGDB
129extern void init_second_port(void);
130#endif
131
132/*
133 * Initialize the next level interrupt handler
134 */
135void __init arch_init_irq(void)
136{
137 clear_c0_status(ST0_IM);
138
139 set_except_vector(0, titan_handle_int);
140 mips_cpu_irq_init(0);
141 rm7k_cpu_irq_init(8);
142 rm9k_cpu_irq_init(12);
143
144#ifdef CONFIG_KGDB
145 /* At this point, initialize the second serial port */
146 init_second_port();
147#endif
148
149#ifdef CONFIG_GDB_CONSOLE
150 register_gdb_console();
151#endif
152}
153
154#ifdef CONFIG_KGDB
155/*
156 * The 16550 DUART has two ports, but is allocated one IRQ
157 * for the serial console. Hence, a generic framework for
158 * serial IRQ routing in place. Currently, just calls the
159 * do_IRQ fuction. But, going in the future, need to check
160 * DUART registers for channel A and B, then decide the
161 * appropriate action
162 */
163asmlinkage void yosemite_kgdb_irq(int irq, struct pt_regs *regs)
164{
165 do_IRQ(irq, regs);
166}
167#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 19:13:40 -0500