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Diffstat (limited to 'arch/mips/pmc-sierra/msp71xx/msp_serial.c')
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_serial.c73
1 files changed, 0 insertions, 73 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index 9de34302e5f4..f7261628d8a6 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -38,68 +38,6 @@
38#include <msp_int.h> 38#include <msp_int.h>
39#include <msp_regs.h> 39#include <msp_regs.h>
40 40
41#ifdef CONFIG_KGDB
42/*
43 * kgdb uses serial port 1 so the console can remain on port 0.
44 * To use port 0 change the definition to read as follows:
45 * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
46 */
47#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
48
49int putDebugChar(char c)
50{
51 volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
52 uint32_t val = (uint32_t)c;
53
54 local_irq_disable();
55 while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
56 uart[0] = val;
57 while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
58 local_irq_enable();
59
60 return 1;
61}
62
63char getDebugChar(void)
64{
65 volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
66 uint32_t val;
67
68 while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
69 val = uart[0];
70
71 return (char)val;
72}
73
74void initDebugPort(unsigned int uartclk, unsigned int baudrate)
75{
76 unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
77
78 /* Enable FIFOs */
79 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
80 UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
81 (char *)DEBUG_PORT_BASE + (UART_FCR * 4));
82
83 /* Select brtc divisor */
84 writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
85
86 /* Store divisor lsb */
87 writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
88
89 /* Store divisor msb */
90 writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
91
92 /* Set 8N1 mode */
93 writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
94
95 /* Disable flow control */
96 writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
97
98 /* Disable receive interrupt(!) */
99 writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
100}
101#endif
102
103void __init msp_serial_setup(void) 41void __init msp_serial_setup(void)
104{ 42{
105 char *s; 43 char *s;
@@ -139,17 +77,6 @@ void __init msp_serial_setup(void)
139 case MACH_MSP7120_FPGA: 77 case MACH_MSP7120_FPGA:
140 /* Enable UART1 on MSP4200 and MSP7120 */ 78 /* Enable UART1 on MSP4200 and MSP7120 */
141 *GPIO_CFG2_REG = 0x00002299; 79 *GPIO_CFG2_REG = 0x00002299;
142
143#ifdef CONFIG_KGDB
144 /* Initialize UART1 for kgdb since PMON doesn't */
145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
146 if( mips_machtype == MACH_MSP4200_FPGA
147 || mips_machtype == MACH_MSP7120_FPGA )
148 initDebugPort(uartclk, 19200);
149 else
150 initDebugPort(uartclk, 57600);
151 }
152#endif
153 break; 80 break;
154 81
155 default: 82 default: