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-rw-r--r--arch/mips/philips/pnx8550/common/Makefile2
-rw-r--r--arch/mips/philips/pnx8550/common/int.c23
-rw-r--r--arch/mips/philips/pnx8550/common/mipsIRQ.S77
3 files changed, 17 insertions, 85 deletions
diff --git a/arch/mips/philips/pnx8550/common/Makefile b/arch/mips/philips/pnx8550/common/Makefile
index 6e38f3bc443c..b7c638166e9f 100644
--- a/arch/mips/philips/pnx8550/common/Makefile
+++ b/arch/mips/philips/pnx8550/common/Makefile
@@ -22,6 +22,6 @@
22# under Linux. 22# under Linux.
23# 23#
24 24
25obj-y := setup.o prom.o mipsIRQ.o int.o reset.o time.o proc.o platform.o 25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
26obj-$(CONFIG_PCI) += pci.o 26obj-$(CONFIG_PCI) += pci.o
27obj-$(CONFIG_KGDB) += gdb_hook.o 27obj-$(CONFIG_KGDB) += gdb_hook.o
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index c500e2d41f2c..39ee6314f627 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -38,8 +38,6 @@
38#include <int.h> 38#include <int.h>
39#include <uart.h> 39#include <uart.h>
40 40
41extern asmlinkage void cp0_irqdispatch(void);
42
43static DEFINE_SPINLOCK(irq_lock); 41static DEFINE_SPINLOCK(irq_lock);
44 42
45/* default prio for interrupts */ 43/* default prio for interrupts */
@@ -55,7 +53,7 @@ static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
55 1 // 70 53 1 // 70
56}; 54};
57 55
58void hw0_irqdispatch(int irq, struct pt_regs *regs) 56static void hw0_irqdispatch(int irq, struct pt_regs *regs)
59{ 57{
60 /* find out which interrupt */ 58 /* find out which interrupt */
61 irq = PNX8550_GIC_VECTOR_0 >> 3; 59 irq = PNX8550_GIC_VECTOR_0 >> 3;
@@ -68,7 +66,7 @@ void hw0_irqdispatch(int irq, struct pt_regs *regs)
68} 66}
69 67
70 68
71void timer_irqdispatch(int irq, struct pt_regs *regs) 69static void timer_irqdispatch(int irq, struct pt_regs *regs)
72{ 70{
73 irq = (0x01c0 & read_c0_config7()) >> 6; 71 irq = (0x01c0 & read_c0_config7()) >> 6;
74 72
@@ -88,6 +86,20 @@ void timer_irqdispatch(int irq, struct pt_regs *regs)
88 } 86 }
89} 87}
90 88
89asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
90{
91 unsigned int pending = read_c0_status() & read_c0_cause();
92
93 if (pending & STATUSF_IP2)
94 do_IRQ(2, regs);
95 else if (pending & STATUSF_IP7) {
96 if (read_c0_config7() & 0x01c0)
97 timer_irqdispatch(7, regs);
98 }
99
100 spurious_interrupt(regs);
101}
102
91static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) 103static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
92{ 104{
93 unsigned long status = read_c0_status(); 105 unsigned long status = read_c0_status();
@@ -223,9 +235,6 @@ void __init arch_init_irq(void)
223 int i; 235 int i;
224 int configPR; 236 int configPR;
225 237
226 /* init of cp0 interrupts */
227 set_except_vector(0, cp0_irqdispatch);
228
229 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 238 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
230 irq_desc[i].handler = &level_irq_type; 239 irq_desc[i].handler = &level_irq_type;
231 pnx8550_ack(i); /* mask the irq just in case */ 240 pnx8550_ack(i); /* mask the irq just in case */
diff --git a/arch/mips/philips/pnx8550/common/mipsIRQ.S b/arch/mips/philips/pnx8550/common/mipsIRQ.S
deleted file mode 100644
index e049a719f83d..000000000000
--- a/arch/mips/philips/pnx8550/common/mipsIRQ.S
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * Copyright (c) 2002 Philips, Inc. All rights.
3 * Copyright (c) 2002 Red Hat, Inc. All rights.
4 *
5 * This software may be freely redistributed under the terms of the
6 * GNU General Public License.
7 *
8 * You should have received a copy of the GNU General Public License
9 * along with this program; if not, write to the Free Software
10 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
11 *
12 * Based upon arch/mips/galileo-boards/ev64240/int-handler.S
13 *
14 */
15#include <asm/asm.h>
16#include <asm/mipsregs.h>
17#include <asm/addrspace.h>
18#include <asm/regdef.h>
19#include <asm/stackframe.h>
20
21/*
22 * cp0_irqdispatch
23 *
24 * Code to handle in-core interrupt exception.
25 */
26
27 .align 5
28 .set reorder
29 .set noat
30 NESTED(cp0_irqdispatch, PT_SIZE, sp)
31 SAVE_ALL
32 CLI
33 .set at
34 mfc0 t0,CP0_CAUSE
35 mfc0 t2,CP0_STATUS
36
37 and t0,t2
38
39 andi t1,t0,STATUSF_IP2 /* int0 hardware line */
40 bnez t1,ll_hw0_irq
41 nop
42
43 andi t1,t0,STATUSF_IP7 /* int5 hardware line */
44 bnez t1,ll_timer_irq
45 nop
46
47 /* wrong alarm or masked ... */
48
49 jal spurious_interrupt
50 nop
51 j ret_from_irq
52 END(cp0_irqdispatch)
53
54 .align 5
55 .set reorder
56ll_hw0_irq:
57 li a0,2
58 move a1,sp
59 jal hw0_irqdispatch
60 nop
61 j ret_from_irq
62 nop
63
64 .align 5
65 .set reorder
66ll_timer_irq:
67 mfc0 t3,CP0_CONFIG,7
68 andi t4,t3,0x01c0
69 beqz t4,ll_timer_out
70 nop
71 li a0,7
72 move a1,sp
73 jal timer_irqdispatch
74 nop
75
76ll_timer_out: j ret_from_irq
77 nop