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-rw-r--r--arch/mips/philips/pnx8550/common/int.c66
1 files changed, 12 insertions, 54 deletions
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 710611615ca2..e4bf494dd435 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -38,8 +38,6 @@
38#include <int.h> 38#include <int.h>
39#include <uart.h> 39#include <uart.h>
40 40
41static DEFINE_SPINLOCK(irq_lock);
42
43/* default prio for interrupts */ 41/* default prio for interrupts */
44/* first one is a no-no so therefore always prio 0 (disabled) */ 42/* first one is a no-no so therefore always prio 0 (disabled) */
45static char gic_prio[PNX8550_INT_GIC_TOTINT] = { 43static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
@@ -149,38 +147,6 @@ static inline void unmask_irq(unsigned int irq_nr)
149 } 147 }
150} 148}
151 149
152#define pnx8550_disable pnx8550_ack
153static void pnx8550_ack(unsigned int irq)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&irq_lock, flags);
158 mask_irq(irq);
159 spin_unlock_irqrestore(&irq_lock, flags);
160}
161
162#define pnx8550_enable pnx8550_unmask
163static void pnx8550_unmask(unsigned int irq)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&irq_lock, flags);
168 unmask_irq(irq);
169 spin_unlock_irqrestore(&irq_lock, flags);
170}
171
172static unsigned int startup_irq(unsigned int irq_nr)
173{
174 pnx8550_unmask(irq_nr);
175 return 0;
176}
177
178static void shutdown_irq(unsigned int irq_nr)
179{
180 pnx8550_ack(irq_nr);
181 return;
182}
183
184int pnx8550_set_gic_priority(int irq, int priority) 150int pnx8550_set_gic_priority(int irq, int priority)
185{ 151{
186 int gic_irq = irq-PNX8550_INT_GIC_MIN; 152 int gic_irq = irq-PNX8550_INT_GIC_MIN;
@@ -192,26 +158,19 @@ int pnx8550_set_gic_priority(int irq, int priority)
192 return prev_priority; 158 return prev_priority;
193} 159}
194 160
195static inline void mask_and_ack_level_irq(unsigned int irq)
196{
197 pnx8550_disable(irq);
198 return;
199}
200
201static void end_irq(unsigned int irq) 161static void end_irq(unsigned int irq)
202{ 162{
203 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { 163 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
204 pnx8550_enable(irq); 164 unmask_irq(irq);
205 } 165 }
206} 166}
207 167
208static struct irq_chip level_irq_type = { 168static struct irq_chip level_irq_type = {
209 .typename = "PNX Level IRQ", 169 .typename = "PNX Level IRQ",
210 .startup = startup_irq, 170 .ack = mask_irq,
211 .shutdown = shutdown_irq, 171 .mask = mask_irq,
212 .enable = pnx8550_enable, 172 .mask_ack = mask_irq,
213 .disable = pnx8550_disable, 173 .unmask = unmask_irq,
214 .ack = mask_and_ack_level_irq,
215 .end = end_irq, 174 .end = end_irq,
216}; 175};
217 176
@@ -233,8 +192,8 @@ void __init arch_init_irq(void)
233 int configPR; 192 int configPR;
234 193
235 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 194 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
236 irq_desc[i].chip = &level_irq_type; 195 set_irq_chip(i, &level_irq_type);
237 pnx8550_ack(i); /* mask the irq just in case */ 196 mask_irq(i); /* mask the irq just in case */
238 } 197 }
239 198
240 /* init of GIC/IPC interrupts */ 199 /* init of GIC/IPC interrupts */
@@ -270,7 +229,7 @@ void __init arch_init_irq(void)
270 /* mask/priority is still 0 so we will not get any 229 /* mask/priority is still 0 so we will not get any
271 * interrupts until it is unmasked */ 230 * interrupts until it is unmasked */
272 231
273 irq_desc[i].chip = &level_irq_type; 232 set_irq_chip(i, &level_irq_type);
274 } 233 }
275 234
276 /* Priority level 0 */ 235 /* Priority level 0 */
@@ -279,20 +238,19 @@ void __init arch_init_irq(void)
279 /* Set int vector table address */ 238 /* Set int vector table address */
280 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 239 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
281 240
282 irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type; 241 set_irq_chip(MIPS_CPU_GIC_IRQ, &level_irq_type);
283 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 242 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
284 243
285 /* init of Timer interrupts */ 244 /* init of Timer interrupts */
286 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { 245 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
287 irq_desc[i].chip = &level_irq_type; 246 set_irq_chip(i, &level_irq_type);
288 }
289 247
290 /* Stop Timer 1-3 */ 248 /* Stop Timer 1-3 */
291 configPR = read_c0_config7(); 249 configPR = read_c0_config7();
292 configPR |= 0x00000038; 250 configPR |= 0x00000038;
293 write_c0_config7(configPR); 251 write_c0_config7(configPR);
294 252
295 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type; 253 set_irq_chip(MIPS_CPU_TIMER_IRQ, &level_irq_type);
296 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 254 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
297} 255}
298 256