11 files changed, 802 insertions, 71 deletions

diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 6523d558ff5a..300591c6278d 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX)		+= pci-bcm47xx.o
 obj-$(CONFIG_BCM63XX)           += pci-bcm63xx.o fixup-bcm63xx.o \
                                         ops-bcm63xx.o
 obj-$(CONFIG_MIPS_ALCHEMY)      += pci-alchemy.o
+obj-$(CONFIG_PCI_AR2315)        += pci-ar2315.o
 obj-$(CONFIG_SOC_AR71XX)        += pci-ar71xx.o
 obj-$(CONFIG_PCI_AR724X)        += pci-ar724x.o
 obj-$(CONFIG_MIPS_PCI_VIRTIO)   += pci-virtio-guest.o
@@ -42,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)	+= pci-bcm1480.o pci-bcm1480ht.o
 obj-$(CONFIG_SNI_RM)            += fixup-sni.o ops-sni.o
 obj-$(CONFIG_LANTIQ)            += fixup-lantiq.o
 obj-$(CONFIG_PCI_LANTIQ)        += pci-lantiq.o ops-lantiq.o
+obj-$(CONFIG_SOC_RT2880)        += pci-rt2880.o
 obj-$(CONFIG_SOC_RT3883)        += pci-rt3883.o
 obj-$(CONFIG_TANBAC_TB0219)     += fixup-tb0219.o
 obj-$(CONFIG_TANBAC_TB0226)     += fixup-tb0226.o
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 13eea696bbe7..d02eb9d16b55 100644
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -469,7 +469,7 @@ static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
 {
         switch (bus->number) {
         case PCIE_BUS_BRIDGE:
-                return (PCI_SLOT(devfn) == 0);
+                return PCI_SLOT(devfn) == 0;
         case PCIE_BUS_DEVICE:
                 if (PCI_SLOT(devfn) == 0)
                         return bcm_pcie_readl(PCIE_DLSTATUS_REG)
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
index a1a7c9f4096e..b9d1fd0ff7e2 100644
--- a/arch/mips/pci/ops-nile4.c
+++ b/arch/mips/pci/ops-nile4.c
@@ -13,8 +13,6 @@
 
 volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
 
-static DEFINE_SPINLOCK(nile4_pci_lock);
-
 static int nile4_pcibios_config_access(unsigned char access_type,
         struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
 {
@@ -76,7 +74,6 @@ static int nile4_pcibios_config_access(unsigned char access_type,
 static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
         int where, int size, u32 *val)
 {
-        unsigned long flags;
         u32 data = 0;
         int err;
 
@@ -85,11 +82,8 @@ static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
         else if ((size == 4) && (where & 3))
                 return PCIBIOS_BAD_REGISTER_NUMBER;
 
-        spin_lock_irqsave(&nile4_pci_lock, flags);
         err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
-                                        &data);
-        spin_unlock_irqrestore(&nile4_pci_lock, flags);
-
+                                          &data);
         if (err)
                 return err;
 
@@ -106,7 +100,6 @@ static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
         int where, int size, u32 val)
 {
-        unsigned long flags;
         u32 data = 0;
         int err;
 
@@ -115,11 +108,8 @@ static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
         else if ((size == 4) && (where & 3))
                 return PCIBIOS_BAD_REGISTER_NUMBER;
 
-        spin_lock_irqsave(&nile4_pci_lock, flags);
         err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
                                           &data);
-        spin_unlock_irqrestore(&nile4_pci_lock, flags);
-
         if (err)
                 return err;
 
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 50034f985be1..dd2d9f7e9412 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -193,8 +193,6 @@ static void pci_proc_init(void)
 }
 #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
 
-static DEFINE_SPINLOCK(bpci_lock);
-
 /*****************************************************************************
  *
  *  STRUCT: pci_io_resource
@@ -368,7 +366,6 @@ int msp_pcibios_config_access(unsigned char access_type,
         struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
         unsigned char bus_num = bus->number;
         unsigned char dev_fn = (unsigned char)devfn;
-        unsigned long flags;
         unsigned long intr;
         unsigned long value;
         static char pciirqflag;
@@ -401,10 +398,7 @@ int msp_pcibios_config_access(unsigned char access_type,
         }
 
 #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
-        local_irq_save(flags);
         vpe_status = dvpe();
-#else
-        spin_lock_irqsave(&bpci_lock, flags);
 #endif
 
         /*
@@ -457,9 +451,6 @@ int msp_pcibios_config_access(unsigned char access_type,
 
 #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
                 evpe(vpe_status);
-                local_irq_restore(flags);
-#else
-                spin_unlock_irqrestore(&bpci_lock, flags);
 #endif
 
                 return -1;
@@ -467,9 +458,6 @@ int msp_pcibios_config_access(unsigned char access_type,
 
 #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
         evpe(vpe_status);
-        local_irq_restore(flags);
-#else
-        spin_unlock_irqrestore(&bpci_lock, flags);
 #endif
 
         return PCIBIOS_SUCCESSFUL;
diff --git a/arch/mips/pci/pci-ar2315.c b/arch/mips/pci/pci-ar2315.c
new file mode 100644
index 000000000000..bd2b3b60da83
--- /dev/null
+++ b/arch/mips/pci/pci-ar2315.c
@@ -0,0 +1,511 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
+ * and interrupt. PCI interface supports MMIO access method, but does not
+ * seem to support I/O ports.
+ *
+ * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
+ * a memory read/write command on the PCI bus. 30 LSBs of address on
+ * the bus are taken from memory read/write request and 2 MSBs are
+ * determined by PCI unit configuration.
+ *
+ * To work with the configuration space instead of memory is necessary set
+ * the CFG_SEL bit in the PCI_MISC_CONFIG register.
+ *
+ * Devices on the bus can perform DMA requests via chip BAR1. PCI host
+ * controller BARs are programmend as if an external device is programmed.
+ * Which means that during configuration, IDSEL pin of the chip should be
+ * asserted.
+ *
+ * We know (and support) only one board that uses the PCI interface -
+ * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
+ * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
+ * and IDSEL pin of AR2315 is connected to AD[16] line.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <asm/paccess.h>
+
+/*
+ * PCI Bus Interface Registers
+ */
+#define AR2315_PCI_1MS_REG              0x0008
+
+#define AR2315_PCI_1MS_MASK             0x3FFFF /* # of AHB clk cycles in 1ms */
+
+#define AR2315_PCI_MISC_CONFIG          0x000c
+
+#define AR2315_PCIMISC_TXD_EN   0x00000001      /* Enable TXD for fragments */
+#define AR2315_PCIMISC_CFG_SEL  0x00000002      /* Mem or Config cycles */
+#define AR2315_PCIMISC_GIG_MASK 0x0000000C      /* bits 31-30 for pci req */
+#define AR2315_PCIMISC_RST_MODE 0x00000030
+#define AR2315_PCIRST_INPUT     0x00000000      /* 4:5=0 rst is input */
+#define AR2315_PCIRST_LOW       0x00000010      /* 4:5=1 rst to GND */
+#define AR2315_PCIRST_HIGH      0x00000020      /* 4:5=2 rst to VDD */
+#define AR2315_PCIGRANT_EN      0x00000000      /* 6:7=0 early grant en */
+#define AR2315_PCIGRANT_FRAME   0x00000040      /* 6:7=1 grant waits 4 frame */
+#define AR2315_PCIGRANT_IDLE    0x00000080      /* 6:7=2 grant waits 4 idle */
+#define AR2315_PCIGRANT_GAP     0x00000000      /* 6:7=2 grant waits 4 idle */
+#define AR2315_PCICACHE_DIS     0x00001000      /* PCI external access cache
+                                                 * disable */
+
+#define AR2315_PCI_OUT_TSTAMP           0x0010
+
+#define AR2315_PCI_UNCACHE_CFG          0x0014
+
+#define AR2315_PCI_IN_EN                0x0100
+
+#define AR2315_PCI_IN_EN0       0x01    /* Enable chain 0 */
+#define AR2315_PCI_IN_EN1       0x02    /* Enable chain 1 */
+#define AR2315_PCI_IN_EN2       0x04    /* Enable chain 2 */
+#define AR2315_PCI_IN_EN3       0x08    /* Enable chain 3 */
+
+#define AR2315_PCI_IN_DIS               0x0104
+
+#define AR2315_PCI_IN_DIS0      0x01    /* Disable chain 0 */
+#define AR2315_PCI_IN_DIS1      0x02    /* Disable chain 1 */
+#define AR2315_PCI_IN_DIS2      0x04    /* Disable chain 2 */
+#define AR2315_PCI_IN_DIS3      0x08    /* Disable chain 3 */
+
+#define AR2315_PCI_IN_PTR               0x0200
+
+#define AR2315_PCI_OUT_EN               0x0400
+
+#define AR2315_PCI_OUT_EN0      0x01    /* Enable chain 0 */
+
+#define AR2315_PCI_OUT_DIS              0x0404
+
+#define AR2315_PCI_OUT_DIS0     0x01    /* Disable chain 0 */
+
+#define AR2315_PCI_OUT_PTR              0x0408
+
+/* PCI interrupt status (write one to clear) */
+#define AR2315_PCI_ISR                  0x0500
+
+#define AR2315_PCI_INT_TX       0x00000001      /* Desc In Completed */
+#define AR2315_PCI_INT_TXOK     0x00000002      /* Desc In OK */
+#define AR2315_PCI_INT_TXERR    0x00000004      /* Desc In ERR */
+#define AR2315_PCI_INT_TXEOL    0x00000008      /* Desc In End-of-List */
+#define AR2315_PCI_INT_RX       0x00000010      /* Desc Out Completed */
+#define AR2315_PCI_INT_RXOK     0x00000020      /* Desc Out OK */
+#define AR2315_PCI_INT_RXERR    0x00000040      /* Desc Out ERR */
+#define AR2315_PCI_INT_RXEOL    0x00000080      /* Desc Out EOL */
+#define AR2315_PCI_INT_TXOOD    0x00000200      /* Desc In Out-of-Desc */
+#define AR2315_PCI_INT_DESCMASK 0x0000FFFF      /* Desc Mask */
+#define AR2315_PCI_INT_EXT      0x02000000      /* Extern PCI INTA */
+#define AR2315_PCI_INT_ABORT    0x04000000      /* PCI bus abort event */
+
+/* PCI interrupt mask */
+#define AR2315_PCI_IMR                  0x0504
+
+/* Global PCI interrupt enable */
+#define AR2315_PCI_IER                  0x0508
+
+#define AR2315_PCI_IER_DISABLE          0x00    /* disable pci interrupts */
+#define AR2315_PCI_IER_ENABLE           0x01    /* enable pci interrupts */
+
+#define AR2315_PCI_HOST_IN_EN           0x0800
+#define AR2315_PCI_HOST_IN_DIS          0x0804
+#define AR2315_PCI_HOST_IN_PTR          0x0810
+#define AR2315_PCI_HOST_OUT_EN          0x0900
+#define AR2315_PCI_HOST_OUT_DIS         0x0904
+#define AR2315_PCI_HOST_OUT_PTR         0x0908
+
+/*
+ * PCI interrupts, which share IP5
+ * Keep ordered according to AR2315_PCI_INT_XXX bits
+ */
+#define AR2315_PCI_IRQ_EXT              25
+#define AR2315_PCI_IRQ_ABORT            26
+#define AR2315_PCI_IRQ_COUNT            27
+
+/* Arbitrary size of memory region to access the configuration space */
+#define AR2315_PCI_CFG_SIZE     0x00100000
+
+#define AR2315_PCI_HOST_SLOT    3
+#define AR2315_PCI_HOST_DEVID   ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
+
+/* ??? access BAR */
+#define AR2315_PCI_HOST_MBAR0           0x10000000
+/* RAM access BAR */
+#define AR2315_PCI_HOST_MBAR1           AR2315_PCI_HOST_SDRAM_BASEADDR
+/* ??? access BAR */
+#define AR2315_PCI_HOST_MBAR2           0x30000000
+
+struct ar2315_pci_ctrl {
+        void __iomem *cfg_mem;
+        void __iomem *mmr_mem;
+        unsigned irq;
+        unsigned irq_ext;
+        struct irq_domain *domain;
+        struct pci_controller pci_ctrl;
+        struct resource mem_res;
+        struct resource io_res;
+};
+
+static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
+{
+        struct pci_controller *hose = bus->sysdata;
+
+        return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
+}
+
+static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
+{
+        return __raw_readl(apc->mmr_mem + reg);
+}
+
+static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
+                                        u32 val)
+{
+        __raw_writel(val, apc->mmr_mem + reg);
+}
+
+static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
+                                       u32 mask, u32 val)
+{
+        u32 ret = ar2315_pci_reg_read(apc, reg);
+
+        ret &= ~mask;
+        ret |= val;
+        ar2315_pci_reg_write(apc, reg, ret);
+}
+
+static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
+                                 int where, int size, u32 *ptr, bool write)
+{
+        int func = PCI_FUNC(devfn);
+        int dev = PCI_SLOT(devfn);
+        u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
+        u32 mask = 0xffffffff >> 8 * (4 - size);
+        u32 sh = (where & 3) * 8;
+        u32 value, isr;
+
+        /* Prevent access past the remapped area */
+        if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /* Clear pending errors */
+        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
+        /* Select Configuration access */
+        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
+                            AR2315_PCIMISC_CFG_SEL);
+
+        mb();   /* PCI must see space change before we begin */
+
+        value = __raw_readl(apc->cfg_mem + addr);
+
+        isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
+
+        if (isr & AR2315_PCI_INT_ABORT)
+                goto exit_err;
+
+        if (write) {
+                value = (value & ~(mask << sh)) | *ptr << sh;
+                __raw_writel(value, apc->cfg_mem + addr);
+                isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
+                if (isr & AR2315_PCI_INT_ABORT)
+                        goto exit_err;
+        } else {
+                *ptr = (value >> sh) & mask;
+        }
+
+        goto exit;
+
+exit_err:
+        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
+        if (!write)
+                *ptr = 0xffffffff;
+
+exit:
+        /* Select Memory access */
+        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
+                            0);
+
+        return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
+                                            PCIBIOS_SUCCESSFUL;
+}
+
+static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
+                                          unsigned devfn, int where, u32 *val)
+{
+        return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
+                                     false);
+}
+
+static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
+                                          unsigned devfn, int where, u32 val)
+{
+        return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
+                                     true);
+}
+
+static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
+                               int size, u32 *value)
+{
+        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
+
+        if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
+}
+
+static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
+                                int size, u32 value)
+{
+        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
+
+        if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
+}
+
+static struct pci_ops ar2315_pci_ops = {
+        .read   = ar2315_pci_cfg_read,
+        .write  = ar2315_pci_cfg_write,
+};
+
+static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
+{
+        unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
+        int res;
+        u32 id;
+
+        res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
+        if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
+                return -ENODEV;
+
+        /* Program MBARs */
+        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
+                                AR2315_PCI_HOST_MBAR0);
+        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
+                                AR2315_PCI_HOST_MBAR1);
+        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
+                                AR2315_PCI_HOST_MBAR2);
+
+        /* Run */
+        ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
+                                PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+                                PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
+                                PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
+
+        return 0;
+}
+
+static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+        struct ar2315_pci_ctrl *apc = irq_get_handler_data(irq);
+        u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
+                      ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
+        unsigned pci_irq = 0;
+
+        if (pending)
+                pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
+
+        if (pci_irq)
+                generic_handle_irq(pci_irq);
+        else
+                spurious_interrupt();
+}
+
+static void ar2315_pci_irq_mask(struct irq_data *d)
+{
+        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
+
+        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
+}
+
+static void ar2315_pci_irq_mask_ack(struct irq_data *d)
+{
+        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
+        u32 m = BIT(d->hwirq);
+
+        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
+        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
+}
+
+static void ar2315_pci_irq_unmask(struct irq_data *d)
+{
+        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
+
+        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
+}
+
+static struct irq_chip ar2315_pci_irq_chip = {
+        .name = "AR2315-PCI",
+        .irq_mask = ar2315_pci_irq_mask,
+        .irq_mask_ack = ar2315_pci_irq_mask_ack,
+        .irq_unmask = ar2315_pci_irq_unmask,
+};
+
+static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
+                              irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
+        irq_set_chip_data(irq, d->host_data);
+        return 0;
+}
+
+static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
+        .map = ar2315_pci_irq_map,
+};
+
+static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
+{
+        ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
+        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
+                            AR2315_PCI_INT_EXT), 0);
+
+        apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
+
+        irq_set_chained_handler(apc->irq, ar2315_pci_irq_handler);
+        irq_set_handler_data(apc->irq, apc);
+
+        /* Clear any pending Abort or external Interrupts
+         * and enable interrupt processing */
+        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
+                                                  AR2315_PCI_INT_EXT);
+        ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
+}
+
+static int ar2315_pci_probe(struct platform_device *pdev)
+{
+        struct ar2315_pci_ctrl *apc;
+        struct device *dev = &pdev->dev;
+        struct resource *res;
+        int irq, err;
+
+        apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
+        if (!apc)
+                return -ENOMEM;
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0)
+                return -EINVAL;
+        apc->irq = irq;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                           "ar2315-pci-ctrl");
+        apc->mmr_mem = devm_ioremap_resource(dev, res);
+        if (IS_ERR(apc->mmr_mem))
+                return PTR_ERR(apc->mmr_mem);
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                           "ar2315-pci-ext");
+        if (!res)
+                return -EINVAL;
+
+        apc->mem_res.name = "AR2315 PCI mem space";
+        apc->mem_res.parent = res;
+        apc->mem_res.start = res->start;
+        apc->mem_res.end = res->end;
+        apc->mem_res.flags = IORESOURCE_MEM;
+
+        /* Remap PCI config space */
+        apc->cfg_mem = devm_ioremap_nocache(dev, res->start,
+                                            AR2315_PCI_CFG_SIZE);
+        if (!apc->cfg_mem) {
+                dev_err(dev, "failed to remap PCI config space\n");
+                return -ENOMEM;
+        }
+
+        /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
+        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
+                            AR2315_PCIMISC_RST_MODE,
+                            AR2315_PCIRST_LOW);
+        msleep(100);
+
+        /* Bring the PCI out of reset */
+        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
+                            AR2315_PCIMISC_RST_MODE,
+                            AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
+
+        ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
+                             0x1E | /* 1GB uncached */
+                             (1 << 5) | /* Enable uncached */
+                             (0x2 << 30) /* Base: 0x80000000 */);
+        ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
+
+        msleep(500);
+
+        err = ar2315_pci_host_setup(apc);
+        if (err)
+                return err;
+
+        apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
+                                            &ar2315_pci_irq_domain_ops, apc);
+        if (!apc->domain) {
+                dev_err(dev, "failed to add IRQ domain\n");
+                return -ENOMEM;
+        }
+
+        ar2315_pci_irq_init(apc);
+
+        /* PCI controller does not support I/O ports */
+        apc->io_res.name = "AR2315 IO space";
+        apc->io_res.start = 0;
+        apc->io_res.end = 0;
+        apc->io_res.flags = IORESOURCE_IO,
+
+        apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
+        apc->pci_ctrl.mem_resource = &apc->mem_res,
+        apc->pci_ctrl.io_resource = &apc->io_res,
+
+        register_pci_controller(&apc->pci_ctrl);
+
+        dev_info(dev, "register PCI controller\n");
+
+        return 0;
+}
+
+static struct platform_driver ar2315_pci_driver = {
+        .probe = ar2315_pci_probe,
+        .driver = {
+                .name = "ar2315-pci",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init ar2315_pci_init(void)
+{
+        return platform_driver_register(&ar2315_pci_driver);
+}
+arch_initcall(ar2315_pci_init);
+
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
+
+        return slot ? 0 : apc->irq_ext;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c
index d471a26dd5f8..2b534aea20e4 100644
--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -50,7 +50,6 @@
 
 struct ar71xx_pci_controller {
         void __iomem *cfg_base;
-        spinlock_t lock;
         int irq;
         int irq_base;
         struct pci_controller pci_ctrl;
@@ -182,7 +181,6 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 {
         struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
         void __iomem *base = apc->cfg_base;
-        unsigned long flags;
         u32 data;
         int err;
         int ret;
@@ -190,8 +188,6 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
         ret = PCIBIOS_SUCCESSFUL;
         data = ~0;
 
-        spin_lock_irqsave(&apc->lock, flags);
-
         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
                                      AR71XX_PCI_CFG_CMD_READ);
         if (err)
@@ -199,8 +195,6 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
         else
                 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
 
-        spin_unlock_irqrestore(&apc->lock, flags);
-
         *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
 
         return ret;
@@ -211,15 +205,12 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 {
         struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
         void __iomem *base = apc->cfg_base;
-        unsigned long flags;
         int err;
         int ret;
 
         value = value << (8 * (where & 3));
         ret = PCIBIOS_SUCCESSFUL;
 
-        spin_lock_irqsave(&apc->lock, flags);
-
         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
                                      AR71XX_PCI_CFG_CMD_WRITE);
         if (err)
@@ -227,8 +218,6 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
         else
                 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
 
-        spin_unlock_irqrestore(&apc->lock, flags);
-
         return ret;
 }
 
@@ -360,8 +349,6 @@ static int ar71xx_pci_probe(struct platform_device *pdev)
         if (!apc)
                 return -ENOMEM;
 
-        spin_lock_init(&apc->lock);
-
         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
         apc->cfg_base = devm_ioremap_resource(&pdev->dev, res);
         if (IS_ERR(apc->cfg_base))
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index 785b2659b519..b7a6fcbb8852 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -9,7 +9,6 @@
  *  by the Free Software Foundation.
  */
 
-#include <linux/spinlock.h>
 #include <linux/irq.h>
 #include <linux/pci.h>
 #include <linux/module.h>
@@ -48,8 +47,6 @@ struct ar724x_pci_controller {
         bool bar0_is_cached;
         u32  bar0_value;
 
-        spinlock_t lock;
-
         struct pci_controller pci_controller;
         struct resource io_res;
         struct resource mem_res;
@@ -75,7 +72,6 @@ pci_bus_to_ar724x_controller(struct pci_bus *bus)
 static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
                                   int where, int size, u32 value)
 {
-        unsigned long flags;
         void __iomem *base;
         u32 data;
         int s;
@@ -86,8 +82,6 @@ static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         base = apc->crp_base;
-
-        spin_lock_irqsave(&apc->lock, flags);
         data = __raw_readl(base + (where & ~3));
 
         switch (size) {
@@ -105,14 +99,12 @@ static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
                 data = value;
                 break;
         default:
-                spin_unlock_irqrestore(&apc->lock, flags);
                 return PCIBIOS_BAD_REGISTER_NUMBER;
         }
 
         __raw_writel(data, base + (where & ~3));
         /* flush write */
         __raw_readl(base + (where & ~3));
-        spin_unlock_irqrestore(&apc->lock, flags);
 
         return PCIBIOS_SUCCESSFUL;
 }
@@ -121,7 +113,6 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
                             int size, uint32_t *value)
 {
         struct ar724x_pci_controller *apc;
-        unsigned long flags;
         void __iomem *base;
         u32 data;
 
@@ -133,8 +124,6 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         base = apc->devcfg_base;
-
-        spin_lock_irqsave(&apc->lock, flags);
         data = __raw_readl(base + (where & ~3));
 
         switch (size) {
@@ -153,13 +142,9 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
         case 4:
                 break;
         default:
-                spin_unlock_irqrestore(&apc->lock, flags);
-
                 return PCIBIOS_BAD_REGISTER_NUMBER;
         }
 
-        spin_unlock_irqrestore(&apc->lock, flags);
-
         if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
             apc->bar0_is_cached) {
                 /* use the cached value */
@@ -175,7 +160,6 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                              int size, uint32_t value)
 {
         struct ar724x_pci_controller *apc;
-        unsigned long flags;
         void __iomem *base;
         u32 data;
         int s;
@@ -209,8 +193,6 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
         }
 
         base = apc->devcfg_base;
-
-        spin_lock_irqsave(&apc->lock, flags);
         data = __raw_readl(base + (where & ~3));
 
         switch (size) {
@@ -228,15 +210,12 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                 data = value;
                 break;
         default:
-                spin_unlock_irqrestore(&apc->lock, flags);
-
                 return PCIBIOS_BAD_REGISTER_NUMBER;
         }
 
         __raw_writel(data, base + (where & ~3));
         /* flush write */
         __raw_readl(base + (where & ~3));
-        spin_unlock_irqrestore(&apc->lock, flags);
 
         return PCIBIOS_SUCCESSFUL;
 }
@@ -380,8 +359,6 @@ static int ar724x_pci_probe(struct platform_device *pdev)
         if (apc->irq < 0)
                 return -EINVAL;
 
-        spin_lock_init(&apc->lock);
-
         res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
         if (!res)
                 return -EINVAL;
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 59cccd95688b..d07e04121cc6 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -708,7 +708,7 @@ static int __init octeon_pci_setup(void)
 
         if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
                                                    -1, NULL, 0)))
-                pr_err("Registation of co_pci_edac failed!\n");
+                pr_err("Registration of co_pci_edac failed!\n");
 
         octeon_pci_dma_init();
 
diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c
new file mode 100644
index 000000000000..a4574947e698
--- /dev/null
+++ b/arch/mips/pci/pci-rt2880.c
@@ -0,0 +1,285 @@
+/*
+ *  Ralink RT288x SoC PCI register definitions
+ *
+ *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+
+#include <asm/mach-ralink/rt288x.h>
+
+#define RT2880_PCI_BASE         0x00440000
+#define RT288X_CPU_IRQ_PCI      4
+
+#define RT2880_PCI_MEM_BASE     0x20000000
+#define RT2880_PCI_MEM_SIZE     0x10000000
+#define RT2880_PCI_IO_BASE      0x00460000
+#define RT2880_PCI_IO_SIZE      0x00010000
+
+#define RT2880_PCI_REG_PCICFG_ADDR      0x00
+#define RT2880_PCI_REG_PCIMSK_ADDR      0x0c
+#define RT2880_PCI_REG_BAR0SETUP_ADDR   0x10
+#define RT2880_PCI_REG_IMBASEBAR0_ADDR  0x18
+#define RT2880_PCI_REG_CONFIG_ADDR      0x20
+#define RT2880_PCI_REG_CONFIG_DATA      0x24
+#define RT2880_PCI_REG_MEMBASE          0x28
+#define RT2880_PCI_REG_IOBASE           0x2c
+#define RT2880_PCI_REG_ID               0x30
+#define RT2880_PCI_REG_CLASS            0x34
+#define RT2880_PCI_REG_SUBID            0x38
+#define RT2880_PCI_REG_ARBCTL           0x80
+
+static void __iomem *rt2880_pci_base;
+static DEFINE_SPINLOCK(rt2880_pci_lock);
+
+static u32 rt2880_pci_reg_read(u32 reg)
+{
+        return readl(rt2880_pci_base + reg);
+}
+
+static void rt2880_pci_reg_write(u32 val, u32 reg)
+{
+        writel(val, rt2880_pci_base + reg);
+}
+
+static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+                                         unsigned int func, unsigned int where)
+{
+        return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+                0x80000000);
+}
+
+static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
+                                  int where, int size, u32 *val)
+{
+        unsigned long flags;
+        u32 address;
+        u32 data;
+
+        address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+                                         PCI_FUNC(devfn), where);
+
+        spin_lock_irqsave(&rt2880_pci_lock, flags);
+        rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+        data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+        spin_unlock_irqrestore(&rt2880_pci_lock, flags);
+
+        switch (size) {
+        case 1:
+                *val = (data >> ((where & 3) << 3)) & 0xff;
+                break;
+        case 2:
+                *val = (data >> ((where & 3) << 3)) & 0xffff;
+                break;
+        case 4:
+                *val = data;
+                break;
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
+                                   int where, int size, u32 val)
+{
+        unsigned long flags;
+        u32 address;
+        u32 data;
+
+        address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+                                         PCI_FUNC(devfn), where);
+
+        spin_lock_irqsave(&rt2880_pci_lock, flags);
+        rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+        data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+
+        switch (size) {
+        case 1:
+                data = (data & ~(0xff << ((where & 3) << 3))) |
+                       (val << ((where & 3) << 3));
+                break;
+        case 2:
+                data = (data & ~(0xffff << ((where & 3) << 3))) |
+                       (val << ((where & 3) << 3));
+                break;
+        case 4:
+                data = val;
+                break;
+        }
+
+        rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
+        spin_unlock_irqrestore(&rt2880_pci_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops rt2880_pci_ops = {
+        .read   = rt2880_pci_config_read,
+        .write  = rt2880_pci_config_write,
+};
+
+static struct resource rt2880_pci_mem_resource = {
+        .name   = "PCI MEM space",
+        .start  = RT2880_PCI_MEM_BASE,
+        .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource rt2880_pci_io_resource = {
+        .name   = "PCI IO space",
+        .start  = RT2880_PCI_IO_BASE,
+        .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct pci_controller rt2880_pci_controller = {
+        .pci_ops        = &rt2880_pci_ops,
+        .mem_resource   = &rt2880_pci_mem_resource,
+        .io_resource    = &rt2880_pci_io_resource,
+};
+
+static inline u32 rt2880_pci_read_u32(unsigned long reg)
+{
+        unsigned long flags;
+        u32 address;
+        u32 ret;
+
+        address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
+
+        spin_lock_irqsave(&rt2880_pci_lock, flags);
+        rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+        ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+        spin_unlock_irqrestore(&rt2880_pci_lock, flags);
+
+        return ret;
+}
+
+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
+{
+        unsigned long flags;
+        u32 address;
+
+        address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
+
+        spin_lock_irqsave(&rt2880_pci_lock, flags);
+        rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+        rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
+        spin_unlock_irqrestore(&rt2880_pci_lock, flags);
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        u16 cmd;
+        int irq = -1;
+
+        if (dev->bus->number != 0)
+                return irq;
+
+        switch (PCI_SLOT(dev->devfn)) {
+        case 0x00:
+                rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
+                (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
+                break;
+        case 0x11:
+                irq = RT288X_CPU_IRQ_PCI;
+                break;
+        default:
+                pr_err("%s:%s[%d] trying to alloc unknown pci irq\n",
+                       __FILE__, __func__, __LINE__);
+                BUG();
+                break;
+        }
+
+        pci_write_config_byte((struct pci_dev *) dev,
+                PCI_CACHE_LINE_SIZE, 0x14);
+        pci_write_config_byte((struct pci_dev *) dev, PCI_LATENCY_TIMER, 0xFF);
+        pci_read_config_word((struct pci_dev *) dev, PCI_COMMAND, &cmd);
+        cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+                PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
+                PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
+        pci_write_config_word((struct pci_dev *) dev, PCI_COMMAND, cmd);
+        pci_write_config_byte((struct pci_dev *) dev, PCI_INTERRUPT_LINE,
+                              dev->irq);
+        return irq;
+}
+
+static int rt288x_pci_probe(struct platform_device *pdev)
+{
+        void __iomem *io_map_base;
+        int i;
+
+        rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
+
+        io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
+        rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
+        set_io_port_base((unsigned long) io_map_base);
+
+        ioport_resource.start = RT2880_PCI_IO_BASE;
+        ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
+
+        rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
+        for (i = 0; i < 0xfffff; i++)
+                ;
+
+        rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
+        rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
+        rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
+        rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
+        rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
+        rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
+        rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
+        rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
+        rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
+
+        rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
+        (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
+
+        register_pci_controller(&rt2880_pci_controller);
+        return 0;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+static const struct of_device_id rt288x_pci_match[] = {
+        { .compatible = "ralink,rt288x-pci" },
+        {},
+};
+MODULE_DEVICE_TABLE(of, rt288x_pci_match);
+
+static struct platform_driver rt288x_pci_driver = {
+        .probe = rt288x_pci_probe,
+        .driver = {
+                .name = "rt288x-pci",
+                .owner = THIS_MODULE,
+                .of_match_table = rt288x_pci_match,
+        },
+};
+
+int __init pcibios_init(void)
+{
+        int ret = platform_driver_register(&rt288x_pci_driver);
+
+        if (ret)
+                pr_info("rt288x-pci: Error registering platform driver!");
+
+        return ret;
+}
+
+arch_initcall(pcibios_init);
diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
index 72919aeef42b..0bcc0b1cfddc 100644
--- a/arch/mips/pci/pci-rt3883.c
+++ b/arch/mips/pci/pci-rt3883.c
@@ -61,7 +61,6 @@
 
 struct rt3883_pci_controller {
         void __iomem *base;
-        spinlock_t lock;
 
         struct device_node *intc_of_node;
         struct irq_domain *irq_domain;
@@ -111,10 +110,8 @@ static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
 
         address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 
-        spin_lock_irqsave(&rpc->lock, flags);
         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
         ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
-        spin_unlock_irqrestore(&rpc->lock, flags);
 
         return ret;
 }
@@ -128,10 +125,8 @@ static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
 
         address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 
-        spin_lock_irqsave(&rpc->lock, flags);
         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
         rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
-        spin_unlock_irqrestore(&rpc->lock, flags);
 }
 
 static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -252,10 +247,8 @@ static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
         address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
                                          PCI_FUNC(devfn), where);
 
-        spin_lock_irqsave(&rpc->lock, flags);
         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
         data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
-        spin_unlock_irqrestore(&rpc->lock, flags);
 
         switch (size) {
         case 1:
@@ -288,7 +281,6 @@ static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
         address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
                                          PCI_FUNC(devfn), where);
 
-        spin_lock_irqsave(&rpc->lock, flags);
         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
         data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 
@@ -307,7 +299,6 @@ static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
         }
 
         rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
-        spin_unlock_irqrestore(&rpc->lock, flags);
 
         return PCIBIOS_SUCCESSFUL;
 }
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
index c10fbf2a19dc..cd8ed09c4f53 100644
--- a/arch/mips/pci/pci-tx4939.c
+++ b/arch/mips/pci/pci-tx4939.c
@@ -103,5 +103,5 @@ void __init tx4939_setup_pcierr_irq(void)
                         tx4927_pcierr_interrupt,
                         0, "PCI error",
                         (void *)TX4939_PCIC_REG))
-                pr_warning("Failed to request irq for PCIERR\n");
+                pr_warn("Failed to request irq for PCIERR\n");
 }