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-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-tx4938.c92
-rw-r--r--arch/mips/pci/ops-tx4938.c198
3 files changed, 291 insertions, 0 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index ea8438b81fed..6956de95a7e8 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -52,5 +52,6 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
52obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 52obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
53obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o 53obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o
54obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o 54obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
55obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
55obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 56obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
56obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 57obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c
new file mode 100644
index 000000000000..f455520ada88
--- /dev/null
+++ b/arch/mips/pci/fixup-tx4938.c
@@ -0,0 +1,92 @@
1/*
2 * Toshiba rbtx4938 pci routines
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/tx4938/rbtx4938.h>
18
19extern struct pci_controller tx4938_pci_controller[];
20
21int pci_get_irq(struct pci_dev *dev, int pin)
22{
23 int irq = pin;
24 u8 slot = PCI_SLOT(dev->devfn);
25 struct pci_controller *controller = (struct pci_controller *)dev->sysdata;
26
27 if (controller == &tx4938_pci_controller[1]) {
28 /* TX4938 PCIC1 */
29 switch (slot) {
30 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
31 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL)
32 return RBTX4938_IRQ_IRC + TX4938_IR_ETH0;
33 break;
34 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
35 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL)
36 return RBTX4938_IRQ_IRC + TX4938_IR_ETH1;
37 break;
38 }
39 return 0;
40 }
41
42 /* IRQ rotation */
43 irq--; /* 0-3 */
44 if (dev->bus->parent == NULL &&
45 (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) {
46 /* PCI CardSlot (IDSEL=A23) */
47 /* PCIA => PCIA (IDSEL=A23) */
48 irq = (irq + 0 + slot) % 4;
49 } else {
50 /* PCI Backplane */
51 irq = (irq + 33 - slot) % 4;
52 }
53 irq++; /* 1-4 */
54
55 switch (irq) {
56 case 1:
57 irq = RBTX4938_IRQ_IOC_PCIA;
58 break;
59 case 2:
60 irq = RBTX4938_IRQ_IOC_PCIB;
61 break;
62 case 3:
63 irq = RBTX4938_IRQ_IOC_PCIC;
64 break;
65 case 4:
66 irq = RBTX4938_IRQ_IOC_PCID;
67 break;
68 }
69 return irq;
70}
71
72int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
73{
74 unsigned char irq = 0;
75
76 irq = pci_get_irq(dev, pin);
77
78 printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
79 dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
80 PCI_FUNC(dev->devfn), irq);
81
82 return irq;
83}
84
85/*
86 * Do platform specific device initialization at pci_enable_device() time
87 */
88int pcibios_plat_dev_init(struct pci_dev *dev)
89{
90 return 0;
91}
92
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c
new file mode 100644
index 000000000000..4c0dcfce5297
--- /dev/null
+++ b/arch/mips/pci/ops-tx4938.c
@@ -0,0 +1,198 @@
1/*
2 * Define the pci_ops for the Toshiba rbtx4938
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/addrspace.h>
18#include <asm/tx4938/rbtx4938.h>
19
20/* initialize in setup */
21struct resource pci_io_resource = {
22 .name = "pci IO space",
23 .start = 0,
24 .end = 0,
25 .flags = IORESOURCE_IO
26};
27
28/* initialize in setup */
29struct resource pci_mem_resource = {
30 .name = "pci memory space",
31 .start = 0,
32 .end = 0,
33 .flags = IORESOURCE_MEM
34};
35
36struct resource tx4938_pcic1_pci_io_resource = {
37 .name = "PCI1 IO",
38 .start = 0,
39 .end = 0,
40 .flags = IORESOURCE_IO
41};
42struct resource tx4938_pcic1_pci_mem_resource = {
43 .name = "PCI1 mem",
44 .start = 0,
45 .end = 0,
46 .flags = IORESOURCE_MEM
47};
48
49static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
50{
51 if (bus > 0) {
52 /* Type 1 configuration */
53 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
54 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
55 } else {
56 if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
57 return -1;
58
59 /* Type 0 configuration */
60 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
61 ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
62 }
63 /* clear M_ABORT and Disable M_ABORT Int. */
64 tx4938_pcicptr->pcistatus =
65 (tx4938_pcicptr->pcistatus & 0x0000ffff) |
66 (PCI_STATUS_REC_MASTER_ABORT << 16);
67 tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
68
69 return 0;
70}
71
72static int check_abort(int flags)
73{
74 int code = PCIBIOS_SUCCESSFUL;
75 /* wait write cycle completion before checking error status */
76 while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
77 ;
78 if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
79 tx4938_pcicptr->pcistatus =
80 (tx4938_pcicptr->
81 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
82 << 16);
83 tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
84 code = PCIBIOS_DEVICE_NOT_FOUND;
85 }
86 return code;
87}
88
89static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
90 int where, int size, u32 * val)
91{
92 int flags, retval, dev, busno, func;
93
94 dev = PCI_SLOT(devfn);
95 func = PCI_FUNC(devfn);
96
97 /* check if the bus is top-level */
98 if (bus->parent != NULL)
99 busno = bus->number;
100 else {
101 busno = 0;
102 }
103
104 if (mkaddr(busno, devfn, where, &flags))
105 return -1;
106
107 switch (size) {
108 case 1:
109 *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
110#ifdef __BIG_ENDIAN
111 ((where & 3) ^ 3));
112#else
113 (where & 3));
114#endif
115 break;
116 case 2:
117 *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
118#ifdef __BIG_ENDIAN
119 ((where & 3) ^ 2));
120#else
121 (where & 3));
122#endif
123 break;
124 case 4:
125 *val = tx4938_pcicptr->g2pcfgdata;
126 break;
127 }
128
129 retval = check_abort(flags);
130 if (retval == PCIBIOS_DEVICE_NOT_FOUND)
131 *val = 0xffffffff;
132
133 return retval;
134}
135
136static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
137 int size, u32 val)
138{
139 int flags, dev, busno, func;
140
141 busno = bus->number;
142 dev = PCI_SLOT(devfn);
143 func = PCI_FUNC(devfn);
144
145 /* check if the bus is top-level */
146 if (bus->parent != NULL) {
147 busno = bus->number;
148 } else {
149 busno = 0;
150 }
151
152 if (mkaddr(busno, devfn, where, &flags))
153 return -1;
154
155 switch (size) {
156 case 1:
157 *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
158#ifdef __BIG_ENDIAN
159 ((where & 3) ^ 3)) = val;
160#else
161 (where & 3)) = val;
162#endif
163 break;
164 case 2:
165 *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
166#ifdef __BIG_ENDIAN
167 ((where & 0x3) ^ 0x2)) = val;
168#else
169 (where & 3)) = val;
170#endif
171 break;
172 case 4:
173 tx4938_pcicptr->g2pcfgdata = val;
174 break;
175 }
176
177 return check_abort(flags);
178}
179
180struct pci_ops tx4938_pci_ops = {
181 tx4938_pcibios_read_config,
182 tx4938_pcibios_write_config
183};
184
185struct pci_controller tx4938_pci_controller[] = {
186 /* h/w only supports devices 0x00 to 0x14 */
187 {
188 .pci_ops = &tx4938_pci_ops,
189 .io_resource = &pci_io_resource,
190 .mem_resource = &pci_mem_resource,
191 },
192 /* h/w only supports devices 0x00 to 0x14 */
193 {
194 .pci_ops = &tx4938_pci_ops,
195 .io_resource = &tx4938_pcic1_pci_io_resource,
196 .mem_resource = &tx4938_pcic1_pci_mem_resource,
197 }
198};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 12:09:52 -0500