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-rw-r--r--arch/mips/pci/fixup-malta.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 2f9e52a1a750..40e920c653cc 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -68,6 +68,7 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
68{ 68{
69 unsigned char reg_val; 69 unsigned char reg_val;
70 u32 reg_val32; 70 u32 reg_val32;
71 u16 reg_val16;
71 /* PIIX PIRQC[A:D] irq mappings */ 72 /* PIIX PIRQC[A:D] irq mappings */
72 static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = { 73 static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
73 0, 0, 0, 3, 74 0, 0, 0, 3,
@@ -107,6 +108,11 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
107 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); 108 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
108 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; 109 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
109 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); 110 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
111
112 /* Enable response to special cycles */
113 pci_read_config_word(pdev, PCI_COMMAND, &reg_val16);
114 pci_write_config_word(pdev, PCI_COMMAND,
115 reg_val16 | PCI_COMMAND_SPECIAL);
110} 116}
111 117
112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, 118DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,