diff options
Diffstat (limited to 'arch/mips/pci')
-rw-r--r-- | arch/mips/pci/fixup-au1000.c | 7 | ||||
-rw-r--r-- | arch/mips/pci/ops-au1000.c | 115 | ||||
-rw-r--r-- | arch/mips/pci/ops-bridge.c | 20 | ||||
-rw-r--r-- | arch/mips/pci/pci-ip27.c | 8 | ||||
-rw-r--r-- | arch/mips/pci/pci-sb1250.c | 8 | ||||
-rw-r--r-- | arch/mips/pci/pci-vr41xx.c | 14 |
6 files changed, 100 insertions, 72 deletions
diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c index 00c36c9dbe0e..e2ddfc49237c 100644 --- a/arch/mips/pci/fixup-au1000.c +++ b/arch/mips/pci/fixup-au1000.c | |||
@@ -1,10 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * BRIEF MODULE DESCRIPTION | 2 | * BRIEF MODULE DESCRIPTION |
3 | * Board specific pci fixups. | 3 | * Board specific PCI fixups. |
4 | * | 4 | * |
5 | * Copyright 2001-2003 MontaVista Software Inc. | 5 | * Copyright 2001-2003, 2008 MontaVista Software Inc. |
6 | * Author: MontaVista Software, Inc. | 6 | * Author: MontaVista Software, Inc. <source@mvista.com> |
7 | * ppopov@mvista.com or source@mvista.com | ||
8 | * | 7 | * |
9 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
10 | * under the terms of the GNU General Public License as published by the | 9 | * under the terms of the GNU General Public License as published by the |
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c index 1314bd58f036..9a57c5ab91dd 100644 --- a/arch/mips/pci/ops-au1000.c +++ b/arch/mips/pci/ops-au1000.c | |||
@@ -1,10 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * BRIEF MODULE DESCRIPTION | 2 | * BRIEF MODULE DESCRIPTION |
3 | * Alchemy/AMD Au1x00 PCI support. | 3 | * Alchemy/AMD Au1xx0 PCI support. |
4 | * | 4 | * |
5 | * Copyright 2001-2003, 2007 MontaVista Software Inc. | 5 | * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. |
6 | * Author: MontaVista Software, Inc. | 6 | * Author: MontaVista Software, Inc. <source@mvista.com> |
7 | * ppopov@mvista.com or source@mvista.com | ||
8 | * | 7 | * |
9 | * Support for all devices (greater than 16) added by David Gathright. | 8 | * Support for all devices (greater than 16) added by David Gathright. |
10 | * | 9 | * |
@@ -28,6 +27,7 @@ | |||
28 | * with this program; if not, write to the Free Software Foundation, Inc., | 27 | * with this program; if not, write to the Free Software Foundation, Inc., |
29 | * 675 Mass Ave, Cambridge, MA 02139, USA. | 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
30 | */ | 29 | */ |
30 | |||
31 | #include <linux/types.h> | 31 | #include <linux/types.h> |
32 | #include <linux/pci.h> | 32 | #include <linux/pci.h> |
33 | #include <linux/kernel.h> | 33 | #include <linux/kernel.h> |
@@ -36,9 +36,9 @@ | |||
36 | 36 | ||
37 | #include <asm/mach-au1x00/au1000.h> | 37 | #include <asm/mach-au1x00/au1000.h> |
38 | 38 | ||
39 | #undef DEBUG | 39 | #undef DEBUG |
40 | #ifdef DEBUG | 40 | #ifdef DEBUG |
41 | #define DBG(x...) printk(x) | 41 | #define DBG(x...) printk(KERN_DEBUG x) |
42 | #else | 42 | #else |
43 | #define DBG(x...) | 43 | #define DBG(x...) |
44 | #endif | 44 | #endif |
@@ -46,7 +46,6 @@ | |||
46 | #define PCI_ACCESS_READ 0 | 46 | #define PCI_ACCESS_READ 0 |
47 | #define PCI_ACCESS_WRITE 1 | 47 | #define PCI_ACCESS_WRITE 1 |
48 | 48 | ||
49 | |||
50 | int (*board_pci_idsel)(unsigned int devsel, int assert); | 49 | int (*board_pci_idsel)(unsigned int devsel, int assert); |
51 | 50 | ||
52 | void mod_wired_entry(int entry, unsigned long entrylo0, | 51 | void mod_wired_entry(int entry, unsigned long entrylo0, |
@@ -92,10 +91,9 @@ void __init au1x_pci_cfg_init(void) | |||
92 | } | 91 | } |
93 | 92 | ||
94 | static int config_access(unsigned char access_type, struct pci_bus *bus, | 93 | static int config_access(unsigned char access_type, struct pci_bus *bus, |
95 | unsigned int dev_fn, unsigned char where, | 94 | unsigned int dev_fn, unsigned char where, u32 *data) |
96 | u32 * data) | ||
97 | { | 95 | { |
98 | #if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 ) | 96 | #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) |
99 | unsigned int device = PCI_SLOT(dev_fn); | 97 | unsigned int device = PCI_SLOT(dev_fn); |
100 | unsigned int function = PCI_FUNC(dev_fn); | 98 | unsigned int function = PCI_FUNC(dev_fn); |
101 | unsigned long offset, status; | 99 | unsigned long offset, status; |
@@ -114,38 +112,36 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, | |||
114 | Au1500_PCI_STATCMD); | 112 | Au1500_PCI_STATCMD); |
115 | au_sync_udelay(1); | 113 | au_sync_udelay(1); |
116 | 114 | ||
117 | /* Allow board vendors to implement their own off-chip idsel. | 115 | /* |
116 | * Allow board vendors to implement their own off-chip IDSEL. | ||
118 | * If it doesn't succeed, may as well bail out at this point. | 117 | * If it doesn't succeed, may as well bail out at this point. |
119 | */ | 118 | */ |
120 | if (board_pci_idsel) { | 119 | if (board_pci_idsel && board_pci_idsel(device, 1) == 0) { |
121 | if (board_pci_idsel(device, 1) == 0) { | 120 | *data = 0xffffffff; |
122 | *data = 0xffffffff; | 121 | local_irq_restore(flags); |
123 | local_irq_restore(flags); | 122 | return -1; |
124 | return -1; | ||
125 | } | ||
126 | } | 123 | } |
127 | 124 | ||
128 | /* setup the config window */ | 125 | /* Setup the config window */ |
129 | if (bus->number == 0) { | 126 | if (bus->number == 0) |
130 | cfg_base = ((1<<device)<<11); | 127 | cfg_base = (1 << device) << 11; |
131 | } else { | 128 | else |
132 | cfg_base = 0x80000000 | (bus->number<<16) | (device<<11); | 129 | cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); |
133 | } | ||
134 | 130 | ||
135 | /* setup the lower bits of the 36 bit address */ | 131 | /* Setup the lower bits of the 36-bit address */ |
136 | offset = (function << 8) | (where & ~0x3); | 132 | offset = (function << 8) | (where & ~0x3); |
137 | /* pick up any address that falls below the page mask */ | 133 | /* Pick up any address that falls below the page mask */ |
138 | offset |= cfg_base & ~PAGE_MASK; | 134 | offset |= cfg_base & ~PAGE_MASK; |
139 | 135 | ||
140 | /* page boundary */ | 136 | /* Page boundary */ |
141 | cfg_base = cfg_base & PAGE_MASK; | 137 | cfg_base = cfg_base & PAGE_MASK; |
142 | 138 | ||
143 | /* | 139 | /* |
144 | * To improve performance, if the current device is the same as | 140 | * To improve performance, if the current device is the same as |
145 | * the last device accessed, we don't touch the TLB. | 141 | * the last device accessed, we don't touch the TLB. |
146 | */ | 142 | */ |
147 | entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; | 143 | entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; |
148 | entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; | 144 | entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; |
149 | if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { | 145 | if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { |
150 | mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, | 146 | mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, |
151 | (unsigned long)pci_cfg_vm->addr, PM_4K); | 147 | (unsigned long)pci_cfg_vm->addr, PM_4K); |
@@ -153,38 +149,37 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, | |||
153 | last_entryLo1 = entryLo1; | 149 | last_entryLo1 = entryLo1; |
154 | } | 150 | } |
155 | 151 | ||
156 | if (access_type == PCI_ACCESS_WRITE) { | 152 | if (access_type == PCI_ACCESS_WRITE) |
157 | au_writel(*data, (int)(pci_cfg_vm->addr + offset)); | 153 | au_writel(*data, (int)(pci_cfg_vm->addr + offset)); |
158 | } else { | 154 | else |
159 | *data = au_readl((int)(pci_cfg_vm->addr + offset)); | 155 | *data = au_readl((int)(pci_cfg_vm->addr + offset)); |
160 | } | 156 | |
161 | au_sync_udelay(2); | 157 | au_sync_udelay(2); |
162 | 158 | ||
163 | DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n", | 159 | DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n", |
164 | access_type, bus->number, device, where, *data, offset); | 160 | access_type, bus->number, device, where, *data, offset); |
165 | 161 | ||
166 | /* check master abort */ | 162 | /* Check master abort */ |
167 | status = au_readl(Au1500_PCI_STATCMD); | 163 | status = au_readl(Au1500_PCI_STATCMD); |
168 | 164 | ||
169 | if (status & (1<<29)) { | 165 | if (status & (1 << 29)) { |
170 | *data = 0xffffffff; | 166 | *data = 0xffffffff; |
171 | error = -1; | 167 | error = -1; |
172 | DBG("Au1x Master Abort\n"); | 168 | DBG("Au1x Master Abort\n"); |
173 | } else if ((status >> 28) & 0xf) { | 169 | } else if ((status >> 28) & 0xf) { |
174 | DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf)); | 170 | DBG("PCI ERR detected: device %u, status %lx\n", |
171 | device, (status >> 28) & 0xf); | ||
175 | 172 | ||
176 | /* clear errors */ | 173 | /* Clear errors */ |
177 | au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD); | 174 | au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD); |
178 | 175 | ||
179 | *data = 0xffffffff; | 176 | *data = 0xffffffff; |
180 | error = -1; | 177 | error = -1; |
181 | } | 178 | } |
182 | 179 | ||
183 | /* Take away the idsel. | 180 | /* Take away the IDSEL. */ |
184 | */ | 181 | if (board_pci_idsel) |
185 | if (board_pci_idsel) { | ||
186 | (void)board_pci_idsel(device, 0); | 182 | (void)board_pci_idsel(device, 0); |
187 | } | ||
188 | 183 | ||
189 | local_irq_restore(flags); | 184 | local_irq_restore(flags); |
190 | return error; | 185 | return error; |
@@ -192,7 +187,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, | |||
192 | } | 187 | } |
193 | 188 | ||
194 | static int read_config_byte(struct pci_bus *bus, unsigned int devfn, | 189 | static int read_config_byte(struct pci_bus *bus, unsigned int devfn, |
195 | int where, u8 * val) | 190 | int where, u8 *val) |
196 | { | 191 | { |
197 | u32 data; | 192 | u32 data; |
198 | int ret; | 193 | int ret; |
@@ -206,9 +201,8 @@ static int read_config_byte(struct pci_bus *bus, unsigned int devfn, | |||
206 | return ret; | 201 | return ret; |
207 | } | 202 | } |
208 | 203 | ||
209 | |||
210 | static int read_config_word(struct pci_bus *bus, unsigned int devfn, | 204 | static int read_config_word(struct pci_bus *bus, unsigned int devfn, |
211 | int where, u16 * val) | 205 | int where, u16 *val) |
212 | { | 206 | { |
213 | u32 data; | 207 | u32 data; |
214 | int ret; | 208 | int ret; |
@@ -221,7 +215,7 @@ static int read_config_word(struct pci_bus *bus, unsigned int devfn, | |||
221 | } | 215 | } |
222 | 216 | ||
223 | static int read_config_dword(struct pci_bus *bus, unsigned int devfn, | 217 | static int read_config_dword(struct pci_bus *bus, unsigned int devfn, |
224 | int where, u32 * val) | 218 | int where, u32 *val) |
225 | { | 219 | { |
226 | int ret; | 220 | int ret; |
227 | 221 | ||
@@ -229,9 +223,8 @@ static int read_config_dword(struct pci_bus *bus, unsigned int devfn, | |||
229 | return ret; | 223 | return ret; |
230 | } | 224 | } |
231 | 225 | ||
232 | static int | 226 | static int write_config_byte(struct pci_bus *bus, unsigned int devfn, |
233 | write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, | 227 | int where, u8 val) |
234 | u8 val) | ||
235 | { | 228 | { |
236 | u32 data = 0; | 229 | u32 data = 0; |
237 | 230 | ||
@@ -239,7 +232,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, | |||
239 | return -1; | 232 | return -1; |
240 | 233 | ||
241 | data = (data & ~(0xff << ((where & 3) << 3))) | | 234 | data = (data & ~(0xff << ((where & 3) << 3))) | |
242 | (val << ((where & 3) << 3)); | 235 | (val << ((where & 3) << 3)); |
243 | 236 | ||
244 | if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) | 237 | if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) |
245 | return -1; | 238 | return -1; |
@@ -247,9 +240,8 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, | |||
247 | return PCIBIOS_SUCCESSFUL; | 240 | return PCIBIOS_SUCCESSFUL; |
248 | } | 241 | } |
249 | 242 | ||
250 | static int | 243 | static int write_config_word(struct pci_bus *bus, unsigned int devfn, |
251 | write_config_word(struct pci_bus *bus, unsigned int devfn, int where, | 244 | int where, u16 val) |
252 | u16 val) | ||
253 | { | 245 | { |
254 | u32 data = 0; | 246 | u32 data = 0; |
255 | 247 | ||
@@ -257,18 +249,16 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where, | |||
257 | return -1; | 249 | return -1; |
258 | 250 | ||
259 | data = (data & ~(0xffff << ((where & 3) << 3))) | | 251 | data = (data & ~(0xffff << ((where & 3) << 3))) | |
260 | (val << ((where & 3) << 3)); | 252 | (val << ((where & 3) << 3)); |
261 | 253 | ||
262 | if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) | 254 | if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) |
263 | return -1; | 255 | return -1; |
264 | 256 | ||
265 | |||
266 | return PCIBIOS_SUCCESSFUL; | 257 | return PCIBIOS_SUCCESSFUL; |
267 | } | 258 | } |
268 | 259 | ||
269 | static int | 260 | static int write_config_dword(struct pci_bus *bus, unsigned int devfn, |
270 | write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, | 261 | int where, u32 val) |
271 | u32 val) | ||
272 | { | 262 | { |
273 | if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) | 263 | if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) |
274 | return -1; | 264 | return -1; |
@@ -277,18 +267,20 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, | |||
277 | } | 267 | } |
278 | 268 | ||
279 | static int config_read(struct pci_bus *bus, unsigned int devfn, | 269 | static int config_read(struct pci_bus *bus, unsigned int devfn, |
280 | int where, int size, u32 * val) | 270 | int where, int size, u32 *val) |
281 | { | 271 | { |
282 | switch (size) { | 272 | switch (size) { |
283 | case 1: { | 273 | case 1: { |
284 | u8 _val; | 274 | u8 _val; |
285 | int rc = read_config_byte(bus, devfn, where, &_val); | 275 | int rc = read_config_byte(bus, devfn, where, &_val); |
276 | |||
286 | *val = _val; | 277 | *val = _val; |
287 | return rc; | 278 | return rc; |
288 | } | 279 | } |
289 | case 2: { | 280 | case 2: { |
290 | u16 _val; | 281 | u16 _val; |
291 | int rc = read_config_word(bus, devfn, where, &_val); | 282 | int rc = read_config_word(bus, devfn, where, &_val); |
283 | |||
292 | *val = _val; | 284 | *val = _val; |
293 | return rc; | 285 | return rc; |
294 | } | 286 | } |
@@ -310,7 +302,6 @@ static int config_write(struct pci_bus *bus, unsigned int devfn, | |||
310 | } | 302 | } |
311 | } | 303 | } |
312 | 304 | ||
313 | |||
314 | struct pci_ops au1x_pci_ops = { | 305 | struct pci_ops au1x_pci_ops = { |
315 | config_read, | 306 | config_read, |
316 | config_write | 307 | config_write |
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c index 1fa09929cd7a..b46b3e211775 100644 --- a/arch/mips/pci/ops-bridge.c +++ b/arch/mips/pci/ops-bridge.c | |||
@@ -14,6 +14,22 @@ | |||
14 | #include <asm/sn/sn0/hub.h> | 14 | #include <asm/sn/sn0/hub.h> |
15 | 15 | ||
16 | /* | 16 | /* |
17 | * Most of the IOC3 PCI config register aren't present | ||
18 | * we emulate what is needed for a normal PCI enumeration | ||
19 | */ | ||
20 | static u32 emulate_ioc3_cfg(int where, int size) | ||
21 | { | ||
22 | if (size == 1 && where == 0x3d) | ||
23 | return 0x01; | ||
24 | else if (size == 2 && where == 0x3c) | ||
25 | return 0x0100; | ||
26 | else if (size == 4 && where == 0x3c) | ||
27 | return 0x00000100; | ||
28 | |||
29 | return 0; | ||
30 | } | ||
31 | |||
32 | /* | ||
17 | * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is | 33 | * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is |
18 | * not really documented, so right now I can't write code which uses it. | 34 | * not really documented, so right now I can't write code which uses it. |
19 | * Therefore we use type 0 accesses for now even though they won't work | 35 | * Therefore we use type 0 accesses for now even though they won't work |
@@ -64,7 +80,7 @@ oh_my_gawd: | |||
64 | * generic PCI code a chance to look at the wrong register. | 80 | * generic PCI code a chance to look at the wrong register. |
65 | */ | 81 | */ |
66 | if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { | 82 | if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { |
67 | *value = 0; | 83 | *value = emulate_ioc3_cfg(where, size); |
68 | return PCIBIOS_SUCCESSFUL; | 84 | return PCIBIOS_SUCCESSFUL; |
69 | } | 85 | } |
70 | 86 | ||
@@ -127,7 +143,7 @@ oh_my_gawd: | |||
127 | * generic PCI code a chance to look at the wrong register. | 143 | * generic PCI code a chance to look at the wrong register. |
128 | */ | 144 | */ |
129 | if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { | 145 | if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { |
130 | *value = 0; | 146 | *value = emulate_ioc3_cfg(where, size); |
131 | return PCIBIOS_SUCCESSFUL; | 147 | return PCIBIOS_SUCCESSFUL; |
132 | } | 148 | } |
133 | 149 | ||
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index bb64828a92fe..a18516925cdd 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c | |||
@@ -47,6 +47,9 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) | |||
47 | static int num_bridges = 0; | 47 | static int num_bridges = 0; |
48 | bridge_t *bridge; | 48 | bridge_t *bridge; |
49 | int slot; | 49 | int slot; |
50 | extern int pci_probe_only; | ||
51 | |||
52 | pci_probe_only = 1; | ||
50 | 53 | ||
51 | printk("a bridge\n"); | 54 | printk("a bridge\n"); |
52 | 55 | ||
@@ -100,6 +103,11 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) | |||
100 | */ | 103 | */ |
101 | bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | | 104 | bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | |
102 | BRIDGE_CTRL_MEM_SWAP; | 105 | BRIDGE_CTRL_MEM_SWAP; |
106 | #ifdef CONFIG_PAGE_SIZE_4KB | ||
107 | bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE; | ||
108 | #else /* 16kB or larger */ | ||
109 | bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE; | ||
110 | #endif | ||
103 | 111 | ||
104 | /* | 112 | /* |
105 | * Hmm... IRIX sets additional bits in the address which | 113 | * Hmm... IRIX sets additional bits in the address which |
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 42e4d2c800fa..2a09ad91ec8c 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c | |||
@@ -207,6 +207,7 @@ struct pci_controller sb1250_controller = { | |||
207 | 207 | ||
208 | static int __init sb1250_pcibios_init(void) | 208 | static int __init sb1250_pcibios_init(void) |
209 | { | 209 | { |
210 | void __iomem *io_map_base; | ||
210 | uint32_t cmdreg; | 211 | uint32_t cmdreg; |
211 | uint64_t reg; | 212 | uint64_t reg; |
212 | extern int pci_probe_only; | 213 | extern int pci_probe_only; |
@@ -253,12 +254,13 @@ static int __init sb1250_pcibios_init(void) | |||
253 | * works correctly with most of Linux's drivers. | 254 | * works correctly with most of Linux's drivers. |
254 | * XXX ehs: Should this happen in PCI Device mode? | 255 | * XXX ehs: Should this happen in PCI Device mode? |
255 | */ | 256 | */ |
256 | |||
257 | set_io_port_base((unsigned long) | ||
258 | ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536)); | ||
259 | isa_slot_offset = (unsigned long) | 257 | isa_slot_offset = (unsigned long) |
260 | ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024); | 258 | ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024); |
261 | 259 | ||
260 | io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024); | ||
261 | sb1250_controller.io_map_base = io_map_base; | ||
262 | set_io_port_base((unsigned long)io_map_base); | ||
263 | |||
262 | #ifdef CONFIG_SIBYTE_HAS_LDT | 264 | #ifdef CONFIG_SIBYTE_HAS_LDT |
263 | /* | 265 | /* |
264 | * Also check the LDT bridge's enable, just in case we didn't | 266 | * Also check the LDT bridge's enable, just in case we didn't |
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c index 33c4f683d067..d1e049b55f34 100644 --- a/arch/mips/pci/pci-vr41xx.c +++ b/arch/mips/pci/pci-vr41xx.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * Copyright (C) 2001-2003 MontaVista Software Inc. | 4 | * Copyright (C) 2001-2003 MontaVista Software Inc. |
5 | * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> | 5 | * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> |
6 | * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 6 | * Copyright (C) 2004-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> |
7 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) | 7 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) |
8 | * | 8 | * |
9 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
@@ -300,6 +300,18 @@ static int __init vr41xx_pciu_init(void) | |||
300 | ioport_resource.end = IO_PORT_RESOURCE_END; | 300 | ioport_resource.end = IO_PORT_RESOURCE_END; |
301 | } | 301 | } |
302 | 302 | ||
303 | if (setup->master_io) { | ||
304 | void __iomem *io_map_base; | ||
305 | struct resource *res = vr41xx_pci_controller.io_resource; | ||
306 | master = setup->master_io; | ||
307 | io_map_base = ioremap(master->bus_base_address, | ||
308 | res->end - res->start + 1); | ||
309 | if (!io_map_base) | ||
310 | return -EBUSY; | ||
311 | |||
312 | vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base; | ||
313 | } | ||
314 | |||
303 | register_pci_controller(&vr41xx_pci_controller); | 315 | register_pci_controller(&vr41xx_pci_controller); |
304 | 316 | ||
305 | return 0; | 317 | return 0; |