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-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/fixup-au1000.c43
-rw-r--r--arch/mips/pci/ops-au1000.c308
-rw-r--r--arch/mips/pci/pci-alchemy.c516
4 files changed, 517 insertions, 353 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 4df879937446..bb82cbdbc62a 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -18,14 +18,13 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
18obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o 18obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
19obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ 19obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
20 ops-bcm63xx.o 20 ops-bcm63xx.o
21obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
21 22
22# 23#
23# These are still pretty much in the old state, watch, go blind. 24# These are still pretty much in the old state, watch, go blind.
24# 25#
25obj-$(CONFIG_LASAT) += pci-lasat.o 26obj-$(CONFIG_LASAT) += pci-lasat.o
26obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 27obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
27obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
28obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
29obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 28obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
30obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o 29obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
31obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o 30obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c
deleted file mode 100644
index e2ddfc49237c..000000000000
--- a/arch/mips/pci/fixup-au1000.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Board specific PCI fixups.
4 *
5 * Copyright 2001-2003, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/pci.h>
30#include <linux/init.h>
31
32extern char irq_tab_alchemy[][5];
33
34int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
35{
36 return irq_tab_alchemy[slot][pin];
37}
38
39/* Do platform specific device initialization at pci_enable_device() time */
40int pcibios_plat_dev_init(struct pci_dev *dev)
41{
42 return 0;
43}
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
deleted file mode 100644
index 9a57c5ab91dd..000000000000
--- a/arch/mips/pci/ops-au1000.c
+++ /dev/null
@@ -1,308 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Alchemy/AMD Au1xx0 PCI support.
4 *
5 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * Support for all devices (greater than 16) added by David Gathright.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/kernel.h>
34#include <linux/init.h>
35#include <linux/vmalloc.h>
36
37#include <asm/mach-au1x00/au1000.h>
38
39#undef DEBUG
40#ifdef DEBUG
41#define DBG(x...) printk(KERN_DEBUG x)
42#else
43#define DBG(x...)
44#endif
45
46#define PCI_ACCESS_READ 0
47#define PCI_ACCESS_WRITE 1
48
49int (*board_pci_idsel)(unsigned int devsel, int assert);
50
51void mod_wired_entry(int entry, unsigned long entrylo0,
52 unsigned long entrylo1, unsigned long entryhi,
53 unsigned long pagemask)
54{
55 unsigned long old_pagemask;
56 unsigned long old_ctx;
57
58 /* Save old context and create impossible VPN2 value */
59 old_ctx = read_c0_entryhi() & 0xff;
60 old_pagemask = read_c0_pagemask();
61 write_c0_index(entry);
62 write_c0_pagemask(pagemask);
63 write_c0_entryhi(entryhi);
64 write_c0_entrylo0(entrylo0);
65 write_c0_entrylo1(entrylo1);
66 tlb_write_indexed();
67 write_c0_entryhi(old_ctx);
68 write_c0_pagemask(old_pagemask);
69}
70
71static struct vm_struct *pci_cfg_vm;
72static int pci_cfg_wired_entry;
73static unsigned long last_entryLo0, last_entryLo1;
74
75/*
76 * We can't ioremap the entire pci config space because it's too large.
77 * Nor can we call ioremap dynamically because some device drivers use
78 * the PCI config routines from within interrupt handlers and that
79 * becomes a problem in get_vm_area(). We use one wired TLB to handle
80 * all config accesses for all busses.
81 */
82void __init au1x_pci_cfg_init(void)
83{
84 /* Reserve a wired entry for PCI config accesses */
85 pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
86 if (!pci_cfg_vm)
87 panic(KERN_ERR "PCI unable to get vm area\n");
88 pci_cfg_wired_entry = read_c0_wired();
89 add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
90 last_entryLo0 = last_entryLo1 = 0xffffffff;
91}
92
93static int config_access(unsigned char access_type, struct pci_bus *bus,
94 unsigned int dev_fn, unsigned char where, u32 *data)
95{
96#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
97 unsigned int device = PCI_SLOT(dev_fn);
98 unsigned int function = PCI_FUNC(dev_fn);
99 unsigned long offset, status;
100 unsigned long cfg_base;
101 unsigned long flags;
102 int error = PCIBIOS_SUCCESSFUL;
103 unsigned long entryLo0, entryLo1;
104
105 if (device > 19) {
106 *data = 0xffffffff;
107 return -1;
108 }
109
110 local_irq_save(flags);
111 au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
112 Au1500_PCI_STATCMD);
113 au_sync_udelay(1);
114
115 /*
116 * Allow board vendors to implement their own off-chip IDSEL.
117 * If it doesn't succeed, may as well bail out at this point.
118 */
119 if (board_pci_idsel && board_pci_idsel(device, 1) == 0) {
120 *data = 0xffffffff;
121 local_irq_restore(flags);
122 return -1;
123 }
124
125 /* Setup the config window */
126 if (bus->number == 0)
127 cfg_base = (1 << device) << 11;
128 else
129 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
130
131 /* Setup the lower bits of the 36-bit address */
132 offset = (function << 8) | (where & ~0x3);
133 /* Pick up any address that falls below the page mask */
134 offset |= cfg_base & ~PAGE_MASK;
135
136 /* Page boundary */
137 cfg_base = cfg_base & PAGE_MASK;
138
139 /*
140 * To improve performance, if the current device is the same as
141 * the last device accessed, we don't touch the TLB.
142 */
143 entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
144 entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
145 if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
146 mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
147 (unsigned long)pci_cfg_vm->addr, PM_4K);
148 last_entryLo0 = entryLo0;
149 last_entryLo1 = entryLo1;
150 }
151
152 if (access_type == PCI_ACCESS_WRITE)
153 au_writel(*data, (int)(pci_cfg_vm->addr + offset));
154 else
155 *data = au_readl((int)(pci_cfg_vm->addr + offset));
156
157 au_sync_udelay(2);
158
159 DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n",
160 access_type, bus->number, device, where, *data, offset);
161
162 /* Check master abort */
163 status = au_readl(Au1500_PCI_STATCMD);
164
165 if (status & (1 << 29)) {
166 *data = 0xffffffff;
167 error = -1;
168 DBG("Au1x Master Abort\n");
169 } else if ((status >> 28) & 0xf) {
170 DBG("PCI ERR detected: device %u, status %lx\n",
171 device, (status >> 28) & 0xf);
172
173 /* Clear errors */
174 au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
175
176 *data = 0xffffffff;
177 error = -1;
178 }
179
180 /* Take away the IDSEL. */
181 if (board_pci_idsel)
182 (void)board_pci_idsel(device, 0);
183
184 local_irq_restore(flags);
185 return error;
186#endif
187}
188
189static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
190 int where, u8 *val)
191{
192 u32 data;
193 int ret;
194
195 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
196 if (where & 1)
197 data >>= 8;
198 if (where & 2)
199 data >>= 16;
200 *val = data & 0xff;
201 return ret;
202}
203
204static int read_config_word(struct pci_bus *bus, unsigned int devfn,
205 int where, u16 *val)
206{
207 u32 data;
208 int ret;
209
210 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
211 if (where & 2)
212 data >>= 16;
213 *val = data & 0xffff;
214 return ret;
215}
216
217static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
218 int where, u32 *val)
219{
220 int ret;
221
222 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
223 return ret;
224}
225
226static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
227 int where, u8 val)
228{
229 u32 data = 0;
230
231 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
232 return -1;
233
234 data = (data & ~(0xff << ((where & 3) << 3))) |
235 (val << ((where & 3) << 3));
236
237 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
238 return -1;
239
240 return PCIBIOS_SUCCESSFUL;
241}
242
243static int write_config_word(struct pci_bus *bus, unsigned int devfn,
244 int where, u16 val)
245{
246 u32 data = 0;
247
248 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
249 return -1;
250
251 data = (data & ~(0xffff << ((where & 3) << 3))) |
252 (val << ((where & 3) << 3));
253
254 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
255 return -1;
256
257 return PCIBIOS_SUCCESSFUL;
258}
259
260static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
261 int where, u32 val)
262{
263 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
264 return -1;
265
266 return PCIBIOS_SUCCESSFUL;
267}
268
269static int config_read(struct pci_bus *bus, unsigned int devfn,
270 int where, int size, u32 *val)
271{
272 switch (size) {
273 case 1: {
274 u8 _val;
275 int rc = read_config_byte(bus, devfn, where, &_val);
276
277 *val = _val;
278 return rc;
279 }
280 case 2: {
281 u16 _val;
282 int rc = read_config_word(bus, devfn, where, &_val);
283
284 *val = _val;
285 return rc;
286 }
287 default:
288 return read_config_dword(bus, devfn, where, val);
289 }
290}
291
292static int config_write(struct pci_bus *bus, unsigned int devfn,
293 int where, int size, u32 val)
294{
295 switch (size) {
296 case 1:
297 return write_config_byte(bus, devfn, where, (u8) val);
298 case 2:
299 return write_config_word(bus, devfn, where, (u16) val);
300 default:
301 return write_config_dword(bus, devfn, where, val);
302 }
303}
304
305struct pci_ops au1x_pci_ops = {
306 config_read,
307 config_write
308};
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
new file mode 100644
index 000000000000..4ee57104e47b
--- /dev/null
+++ b/arch/mips/pci/pci-alchemy.c
@@ -0,0 +1,516 @@
1/*
2 * Alchemy PCI host mode support.
3 *
4 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * Support for all devices (greater than 16) added by David Gathright.
8 */
9
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/platform_device.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/vmalloc.h>
16
17#include <asm/mach-au1x00/au1000.h>
18
19#ifdef CONFIG_DEBUG_PCI
20#define DBG(x...) printk(KERN_DEBUG x)
21#else
22#define DBG(x...) do {} while (0)
23#endif
24
25#define PCI_ACCESS_READ 0
26#define PCI_ACCESS_WRITE 1
27
28struct alchemy_pci_context {
29 struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
30 void __iomem *regs; /* ctrl base */
31 /* tools for wired entry for config space access */
32 unsigned long last_elo0;
33 unsigned long last_elo1;
34 int wired_entry;
35 struct vm_struct *pci_cfg_vm;
36
37 unsigned long pm[12];
38
39 int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
40 int (*board_pci_idsel)(unsigned int devsel, int assert);
41};
42
43/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
44 * in arch/mips/alchemy/common/setup.c
45 */
46static struct resource alchemy_pci_def_memres = {
47 .start = ALCHEMY_PCI_MEMWIN_START,
48 .end = ALCHEMY_PCI_MEMWIN_END,
49 .name = "PCI memory space",
50 .flags = IORESOURCE_MEM
51};
52
53static struct resource alchemy_pci_def_iores = {
54 .start = ALCHEMY_PCI_IOWIN_START,
55 .end = ALCHEMY_PCI_IOWIN_END,
56 .name = "PCI IO space",
57 .flags = IORESOURCE_IO
58};
59
60static void mod_wired_entry(int entry, unsigned long entrylo0,
61 unsigned long entrylo1, unsigned long entryhi,
62 unsigned long pagemask)
63{
64 unsigned long old_pagemask;
65 unsigned long old_ctx;
66
67 /* Save old context and create impossible VPN2 value */
68 old_ctx = read_c0_entryhi() & 0xff;
69 old_pagemask = read_c0_pagemask();
70 write_c0_index(entry);
71 write_c0_pagemask(pagemask);
72 write_c0_entryhi(entryhi);
73 write_c0_entrylo0(entrylo0);
74 write_c0_entrylo1(entrylo1);
75 tlb_write_indexed();
76 write_c0_entryhi(old_ctx);
77 write_c0_pagemask(old_pagemask);
78}
79
80static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx)
81{
82 ctx->wired_entry = read_c0_wired();
83 add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
84 ctx->last_elo0 = ctx->last_elo1 = ~0;
85}
86
87static int config_access(unsigned char access_type, struct pci_bus *bus,
88 unsigned int dev_fn, unsigned char where, u32 *data)
89{
90 struct alchemy_pci_context *ctx = bus->sysdata;
91 unsigned int device = PCI_SLOT(dev_fn);
92 unsigned int function = PCI_FUNC(dev_fn);
93 unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r;
94 int error = PCIBIOS_SUCCESSFUL;
95
96 if (device > 19) {
97 *data = 0xffffffff;
98 return -1;
99 }
100
101 /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
102 * on resume, clearing our wired entry. Unfortunately the ->resume()
103 * callback is called way way way too late (and ->suspend() too early)
104 * to have them destroy and recreate it. Instead just test if c0_wired
105 * is now lower than the index we retrieved before suspending and then
106 * recreate the entry if necessary. Of course this is totally bonkers
107 * and breaks as soon as someone else adds another wired entry somewhere
108 * else. Anyone have any ideas how to handle this better?
109 */
110 if (unlikely(read_c0_wired() < ctx->wired_entry))
111 alchemy_pci_wired_entry(ctx);
112
113 local_irq_save(flags);
114 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
115 r |= PCI_STATCMD_STATUS(0x2000);
116 __raw_writel(r, ctx->regs + PCI_REG_STATCMD);
117 wmb();
118
119 /* Allow board vendors to implement their own off-chip IDSEL.
120 * If it doesn't succeed, may as well bail out at this point.
121 */
122 if (ctx->board_pci_idsel(device, 1) == 0) {
123 *data = 0xffffffff;
124 local_irq_restore(flags);
125 return -1;
126 }
127
128 /* Setup the config window */
129 if (bus->number == 0)
130 cfg_base = (1 << device) << 11;
131 else
132 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
133
134 /* Setup the lower bits of the 36-bit address */
135 offset = (function << 8) | (where & ~0x3);
136 /* Pick up any address that falls below the page mask */
137 offset |= cfg_base & ~PAGE_MASK;
138
139 /* Page boundary */
140 cfg_base = cfg_base & PAGE_MASK;
141
142 /* To improve performance, if the current device is the same as
143 * the last device accessed, we don't touch the TLB.
144 */
145 entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
146 entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
147 if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) {
148 mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1,
149 (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
150 ctx->last_elo0 = entryLo0;
151 ctx->last_elo1 = entryLo1;
152 }
153
154 if (access_type == PCI_ACCESS_WRITE)
155 __raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
156 else
157 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
158 wmb();
159
160 DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n",
161 access_type, bus->number, device, where, *data, offset);
162
163 /* check for errors, master abort */
164 status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
165 if (status & (1 << 29)) {
166 *data = 0xffffffff;
167 error = -1;
168 DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
169 access_type, bus->number, device);
170 } else if ((status >> 28) & 0xf) {
171 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
172 device, (status >> 28) & 0xf);
173
174 /* clear errors */
175 __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
176
177 *data = 0xffffffff;
178 error = -1;
179 }
180
181 /* Take away the IDSEL. */
182 (void)ctx->board_pci_idsel(device, 0);
183
184 local_irq_restore(flags);
185 return error;
186}
187
188static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
189 int where, u8 *val)
190{
191 u32 data;
192 int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
193
194 if (where & 1)
195 data >>= 8;
196 if (where & 2)
197 data >>= 16;
198 *val = data & 0xff;
199 return ret;
200}
201
202static int read_config_word(struct pci_bus *bus, unsigned int devfn,
203 int where, u16 *val)
204{
205 u32 data;
206 int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
207
208 if (where & 2)
209 data >>= 16;
210 *val = data & 0xffff;
211 return ret;
212}
213
214static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
215 int where, u32 *val)
216{
217 return config_access(PCI_ACCESS_READ, bus, devfn, where, val);
218}
219
220static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
221 int where, u8 val)
222{
223 u32 data = 0;
224
225 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
226 return -1;
227
228 data = (data & ~(0xff << ((where & 3) << 3))) |
229 (val << ((where & 3) << 3));
230
231 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
232 return -1;
233
234 return PCIBIOS_SUCCESSFUL;
235}
236
237static int write_config_word(struct pci_bus *bus, unsigned int devfn,
238 int where, u16 val)
239{
240 u32 data = 0;
241
242 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
243 return -1;
244
245 data = (data & ~(0xffff << ((where & 3) << 3))) |
246 (val << ((where & 3) << 3));
247
248 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
249 return -1;
250
251 return PCIBIOS_SUCCESSFUL;
252}
253
254static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
255 int where, u32 val)
256{
257 return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val);
258}
259
260static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn,
261 int where, int size, u32 *val)
262{
263 switch (size) {
264 case 1: {
265 u8 _val;
266 int rc = read_config_byte(bus, devfn, where, &_val);
267
268 *val = _val;
269 return rc;
270 }
271 case 2: {
272 u16 _val;
273 int rc = read_config_word(bus, devfn, where, &_val);
274
275 *val = _val;
276 return rc;
277 }
278 default:
279 return read_config_dword(bus, devfn, where, val);
280 }
281}
282
283static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 val)
285{
286 switch (size) {
287 case 1:
288 return write_config_byte(bus, devfn, where, (u8) val);
289 case 2:
290 return write_config_word(bus, devfn, where, (u16) val);
291 default:
292 return write_config_dword(bus, devfn, where, val);
293 }
294}
295
296static struct pci_ops alchemy_pci_ops = {
297 .read = alchemy_pci_read,
298 .write = alchemy_pci_write,
299};
300
301static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
302{
303 return 1; /* success */
304}
305
306static int __devinit alchemy_pci_probe(struct platform_device *pdev)
307{
308 struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
309 struct alchemy_pci_context *ctx;
310 void __iomem *virt_io;
311 unsigned long val;
312 struct resource *r;
313 int ret;
314
315 /* need at least PCI IRQ mapping table */
316 if (!pd) {
317 dev_err(&pdev->dev, "need platform data for PCI setup\n");
318 ret = -ENODEV;
319 goto out;
320 }
321
322 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
323 if (!ctx) {
324 dev_err(&pdev->dev, "no memory for pcictl context\n");
325 ret = -ENOMEM;
326 goto out;
327 }
328
329 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
330 if (!r) {
331 dev_err(&pdev->dev, "no pcictl ctrl regs resource\n");
332 ret = -ENODEV;
333 goto out1;
334 }
335
336 if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
337 dev_err(&pdev->dev, "cannot claim pci regs\n");
338 ret = -ENODEV;
339 goto out1;
340 }
341
342 ctx->regs = ioremap_nocache(r->start, resource_size(r));
343 if (!ctx->regs) {
344 dev_err(&pdev->dev, "cannot map pci regs\n");
345 ret = -ENODEV;
346 goto out2;
347 }
348
349 /* map parts of the PCI IO area */
350 /* REVISIT: if this changes with a newer variant (doubt it) make this
351 * a platform resource.
352 */
353 virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000);
354 if (!virt_io) {
355 dev_err(&pdev->dev, "cannot remap pci io space\n");
356 ret = -ENODEV;
357 goto out3;
358 }
359 ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
360
361#ifdef CONFIG_DMA_NONCOHERENT
362 /* Au1500 revisions older than AD have borked coherent PCI */
363 if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
364 (read_c0_prid() < 0x01030202)) {
365 val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
366 val |= PCI_CONFIG_NC;
367 __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
368 wmb();
369 dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n");
370 }
371#endif
372
373 if (pd->board_map_irq)
374 ctx->board_map_irq = pd->board_map_irq;
375
376 if (pd->board_pci_idsel)
377 ctx->board_pci_idsel = pd->board_pci_idsel;
378 else
379 ctx->board_pci_idsel = alchemy_pci_def_idsel;
380
381 /* fill in relevant pci_controller members */
382 ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops;
383 ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres;
384 ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores;
385
386 /* we can't ioremap the entire pci config space because it's too large,
387 * nor can we dynamically ioremap it because some drivers use the
388 * PCI config routines from within atomic contex and that becomes a
389 * problem in get_vm_area(). Instead we use one wired TLB entry to
390 * handle all config accesses for all busses.
391 */
392 ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
393 if (!ctx->pci_cfg_vm) {
394 dev_err(&pdev->dev, "unable to get vm area\n");
395 ret = -ENOMEM;
396 goto out4;
397 }
398 ctx->wired_entry = 8192; /* impossibly high value */
399
400 set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
401
402 /* board may want to modify bits in the config register, do it now */
403 val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
404 val &= ~pd->pci_cfg_clr;
405 val |= pd->pci_cfg_set;
406 val &= ~PCI_CONFIG_PD; /* clear disable bit */
407 __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
408 wmb();
409
410 platform_set_drvdata(pdev, ctx);
411 register_pci_controller(&ctx->alchemy_pci_ctrl);
412
413 return 0;
414
415out4:
416 iounmap(virt_io);
417out3:
418 iounmap(ctx->regs);
419out2:
420 release_mem_region(r->start, resource_size(r));
421out1:
422 kfree(ctx);
423out:
424 return ret;
425}
426
427
428#ifdef CONFIG_PM
429/* save PCI controller register contents. */
430static int alchemy_pci_suspend(struct device *dev)
431{
432 struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
433
434 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
435 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
436 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
437 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
438 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
439 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
440 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
441 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
442 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
443 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
444 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
445 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
446
447 return 0;
448}
449
450static int alchemy_pci_resume(struct device *dev)
451{
452 struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
453
454 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
455 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
456 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
457 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
458 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
459 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
460 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
461 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
462 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
463 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
464 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
465 wmb();
466 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
467 wmb();
468
469 return 0;
470}
471
472static const struct dev_pm_ops alchemy_pci_pmops = {
473 .suspend = alchemy_pci_suspend,
474 .resume = alchemy_pci_resume,
475};
476
477#define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops)
478
479#else
480#define ALCHEMY_PCICTL_PM NULL
481#endif
482
483static struct platform_driver alchemy_pcictl_driver = {
484 .probe = alchemy_pci_probe,
485 .driver = {
486 .name = "alchemy-pci",
487 .owner = THIS_MODULE,
488 .pm = ALCHEMY_PCICTL_PM,
489 },
490};
491
492static int __init alchemy_pci_init(void)
493{
494 /* Au1500/Au1550 have PCI */
495 switch (alchemy_get_cputype()) {
496 case ALCHEMY_CPU_AU1500:
497 case ALCHEMY_CPU_AU1550:
498 return platform_driver_register(&alchemy_pcictl_driver);
499 }
500 return 0;
501}
502arch_initcall(alchemy_pci_init);
503
504
505int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
506{
507 struct alchemy_pci_context *ctx = dev->sysdata;
508 if (ctx && ctx->board_map_irq)
509 return ctx->board_map_irq(dev, slot, pin);
510 return -1;
511}
512
513int pcibios_plat_dev_init(struct pci_dev *dev)
514{
515 return 0;
516}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 08:57:18 -0500