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-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-ddb5477.c78
-rw-r--r--arch/mips/pci/fixup-ocelot.c75
-rw-r--r--arch/mips/pci/fixup-rbtx4927.c2
-rw-r--r--arch/mips/pci/fixup-tx4938.c2
-rw-r--r--arch/mips/pci/ops-ddb5477.c278
-rw-r--r--arch/mips/pci/ops-emma2rh.c2
-rw-r--r--arch/mips/pci/ops-pnx8550.c12
-rw-r--r--arch/mips/pci/pci-ddb5477.c207
-rw-r--r--arch/mips/pci/pci-ocelot.c107
10 files changed, 9 insertions, 756 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c58bd3d036f4..4ee6800e67e6 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
19# These are still pretty much in the old state, watch, go blind. 19# These are still pretty much in the old state, watch, go blind.
20# 20#
21obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o 21obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
22obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
23obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 22obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
24obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 23obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
25obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 24obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
@@ -27,7 +26,6 @@ obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
27obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 26obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
28obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o 27obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
29obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 28obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
30obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
31obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 29obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
32obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 30obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
33obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o 31obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c
deleted file mode 100644
index 2f1444e60654..000000000000
--- a/arch/mips/pci/fixup-ddb5477.c
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Board specific pci fixups.
5 *
6 * Copyright 2001, 2002, 2003 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/types.h>
31#include <linux/pci.h>
32#include <linux/kernel.h>
33#include <linux/init.h>
34
35static void ddb5477_fixup(struct pci_dev *dev)
36{
37 u8 old;
38
39 printk(KERN_NOTICE "Enabling ALI M1533/35 PS2 keyboard/mouse.\n");
40 pci_read_config_byte(dev, 0x41, &old);
41 pci_write_config_byte(dev, 0x41, old | 0xd0);
42}
43
44DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533,
45 ddb5477_fixup);
46DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1535,
47 ddb5477_fixup);
48
49/*
50 * Fixup baseboard AMD chip so that tx does not underflow.
51 * bcr_18 |= 0x0800
52 * This sets NOUFLO bit which makes tx not start until whole pkt
53 * is fetched to the chip.
54 */
55#define PCNET32_WIO_RDP 0x10
56#define PCNET32_WIO_RAP 0x12
57#define PCNET32_WIO_RESET 0x14
58#define PCNET32_WIO_BDP 0x16
59
60static void ddb5477_amd_lance_fixup(struct pci_dev *dev)
61{
62 unsigned long ioaddr;
63 u16 temp;
64
65 ioaddr = pci_resource_start(dev, 0);
66
67 inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */
68
69 /* bcr_18 |= 0x0800 */
70 outw(18, ioaddr + PCNET32_WIO_RAP);
71 temp = inw(ioaddr + PCNET32_WIO_BDP);
72 temp |= 0x0800;
73 outw(18, ioaddr + PCNET32_WIO_RAP);
74 outw(temp, ioaddr + PCNET32_WIO_BDP);
75}
76
77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE,
78 ddb5477_amd_lance_fixup);
diff --git a/arch/mips/pci/fixup-ocelot.c b/arch/mips/pci/fixup-ocelot.c
deleted file mode 100644
index 99629bd047ce..000000000000
--- a/arch/mips/pci/fixup-ocelot.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/gt64120/momenco_ocelot/pci.c
6 * Board-specific PCI routines for gt64120 controller.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/types.h>
14#include <linux/pci.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <asm/pci.h>
18
19
20void __devinit pcibios_fixup_bus(struct pci_bus *bus)
21{
22 struct pci_bus *current_bus = bus;
23 struct pci_dev *devices;
24 struct list_head *devices_link;
25 u16 cmd;
26
27 list_for_each(devices_link, &(current_bus->devices)) {
28
29 devices = pci_dev_b(devices_link);
30 if (devices == NULL)
31 continue;
32
33 if (PCI_SLOT(devices->devfn) == 1) {
34 /*
35 * Slot 1 is primary ether port, i82559
36 * we double-check against that assumption
37 */
38 if ((devices->vendor != 0x8086) ||
39 (devices->device != 0x1209)) {
40 panic("pcibios_fixup_bus: found "
41 "unexpected PCI device in slot 1.");
42 }
43 devices->irq = 2; /* irq_nr is 2 for INT0 */
44 } else if (PCI_SLOT(devices->devfn) == 2) {
45 /*
46 * Slot 2 is secondary ether port, i21143
47 * we double-check against that assumption
48 */
49 if ((devices->vendor != 0x1011) ||
50 (devices->device != 0x19)) {
51 panic("galileo_pcibios_fixup_bus: "
52 "found unexpected PCI device in slot 2.");
53 }
54 devices->irq = 3; /* irq_nr is 3 for INT1 */
55 } else if (PCI_SLOT(devices->devfn) == 4) {
56 /* PMC Slot 1 */
57 devices->irq = 8; /* irq_nr is 8 for INT6 */
58 } else if (PCI_SLOT(devices->devfn) == 5) {
59 /* PMC Slot 1 */
60 devices->irq = 9; /* irq_nr is 9 for INT7 */
61 } else {
62 /* We don't have assign interrupts for other devices. */
63 devices->irq = 0xff;
64 }
65
66 /* Assign an interrupt number for the device */
67 bus->ops->write_byte(devices, PCI_INTERRUPT_LINE,
68 devices->irq);
69
70 /* enable master */
71 bus->ops->read_word(devices, PCI_COMMAND, &cmd);
72 cmd |= PCI_COMMAND_MASTER;
73 bus->ops->write_word(devices, PCI_COMMAND, cmd);
74 }
75}
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index 3cdbecb8e714..7450c335b387 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -79,7 +79,7 @@ static unsigned char backplane_pci_irq[4][4] = {
79 TX4927_IRQ_IOC_PCIC} 79 TX4927_IRQ_IOC_PCIC}
80}; 80};
81 81
82int pci_get_irq(struct pci_dev *dev, int pin) 82static int pci_get_irq(const struct pci_dev *dev, int pin)
83{ 83{
84 unsigned char irq = pin; 84 unsigned char irq = pin;
85 85
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c
index 2485f47dfe6f..f2ba06ee0c10 100644
--- a/arch/mips/pci/fixup-tx4938.c
+++ b/arch/mips/pci/fixup-tx4938.c
@@ -18,7 +18,7 @@
18 18
19extern struct pci_controller tx4938_pci_controller[]; 19extern struct pci_controller tx4938_pci_controller[];
20 20
21int pci_get_irq(struct pci_dev *dev, int pin) 21static int pci_get_irq(const struct pci_dev *dev, int pin)
22{ 22{
23 int irq = pin; 23 int irq = pin;
24 u8 slot = PCI_SLOT(dev->devfn); 24 u8 slot = PCI_SLOT(dev->devfn);
diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c
deleted file mode 100644
index 8e57d4c5d90f..000000000000
--- a/arch/mips/pci/ops-ddb5477.c
+++ /dev/null
@@ -1,278 +0,0 @@
1/***********************************************************************
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5477/pci_ops.c
6 * Define the pci_ops for DB5477.
7 *
8 * Much of the code is derived from the original DDB5074 port by
9 * Geert Uytterhoeven <geert@sonycom.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 ***********************************************************************
16 */
17
18/*
19 * DDB5477 has two PCI channels, external PCI and IOPIC (internal)
20 * Therefore we provide two sets of pci_ops.
21 */
22#include <linux/pci.h>
23#include <linux/kernel.h>
24#include <linux/types.h>
25
26#include <asm/addrspace.h>
27#include <asm/debug.h>
28
29#include <asm/ddb5xxx/ddb5xxx.h>
30
31/*
32 * config_swap structure records what set of pdar/pmr are used
33 * to access pci config space. It also provides a place hold the
34 * original values for future restoring.
35 */
36struct pci_config_swap {
37 u32 pdar;
38 u32 pmr;
39 u32 config_base;
40 u32 config_size;
41 u32 pdar_backup;
42 u32 pmr_backup;
43};
44
45/*
46 * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI.
47 */
48struct pci_config_swap ext_pci_swap = {
49 DDB_PCIW0,
50 DDB_PCIINIT00,
51 DDB_PCI0_CONFIG_BASE,
52 DDB_PCI0_CONFIG_SIZE
53};
54struct pci_config_swap io_pci_swap = {
55 DDB_IOPCIW0,
56 DDB_PCIINIT01,
57 DDB_PCI1_CONFIG_BASE,
58 DDB_PCI1_CONFIG_SIZE
59};
60
61
62/*
63 * access config space
64 */
65static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
66 u32 slot_num)
67{
68 u32 pci_addr = 0;
69 u32 pciinit_offset = 0;
70 u32 virt_addr;
71 u32 option;
72
73 /* minimum pdar (window) size is 2MB */
74 db_assert(swap->config_size >= (2 << 20));
75
76 db_assert(slot_num < (1 << 5));
77 db_assert(bus < (1 << 8));
78
79 /* backup registers */
80 swap->pdar_backup = ddb_in32(swap->pdar);
81 swap->pmr_backup = ddb_in32(swap->pmr);
82
83 /* set the pdar (pci window) register */
84 ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
85 0, /* not on local memory bus */
86 0); /* not visible from PCI bus (N/A) */
87
88 /*
89 * calcuate the absolute pci config addr;
90 * according to the spec, we start scanning from adr:11 (0x800)
91 */
92 if (bus == 0) {
93 /* type 0 config */
94 pci_addr = 0x800 << slot_num;
95 } else {
96 /* type 1 config */
97 pci_addr = (bus << 16) | (slot_num << 11);
98 }
99
100 /*
101 * if pci_addr is less than pci config window size, we set
102 * pciinit_offset to 0 and adjust the virt_address.
103 * Otherwise we will try to adjust pciinit_offset.
104 */
105 if (pci_addr < swap->config_size) {
106 virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
107 pciinit_offset = 0;
108 } else {
109 db_assert((pci_addr & (swap->config_size - 1)) == 0);
110 virt_addr = KSEG1ADDR(swap->config_base);
111 pciinit_offset = pci_addr;
112 }
113
114 /* set the pmr register */
115 option = DDB_PCI_ACCESS_32;
116 if (bus != 0)
117 option |= DDB_PCI_CFGTYPE1;
118 ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
119
120 return virt_addr;
121}
122
123static inline void ddb_close_config_base(struct pci_config_swap *swap)
124{
125 ddb_out32(swap->pdar, swap->pdar_backup);
126 ddb_out32(swap->pmr, swap->pmr_backup);
127}
128
129static int read_config_dword(struct pci_config_swap *swap,
130 struct pci_bus *bus, u32 devfn, u32 where,
131 u32 * val)
132{
133 u32 bus_num, slot_num, func_num;
134 u32 base;
135
136 db_assert((where & 3) == 0);
137 db_assert(where < (1 << 8));
138
139 /* check if the bus is top-level */
140 if (bus->parent != NULL) {
141 bus_num = bus->number;
142 db_assert(bus_num != 0);
143 } else {
144 bus_num = 0;
145 }
146
147 slot_num = PCI_SLOT(devfn);
148 func_num = PCI_FUNC(devfn);
149 base = ddb_access_config_base(swap, bus_num, slot_num);
150 *val = *(volatile u32 *) (base + (func_num << 8) + where);
151 ddb_close_config_base(swap);
152 return PCIBIOS_SUCCESSFUL;
153}
154
155static int read_config_word(struct pci_config_swap *swap,
156 struct pci_bus *bus, u32 devfn, u32 where,
157 u16 * val)
158{
159 int status;
160 u32 result;
161
162 db_assert((where & 1) == 0);
163
164 status = read_config_dword(swap, bus, devfn, where & ~3, &result);
165 if (where & 2)
166 result >>= 16;
167 *val = result & 0xffff;
168 return status;
169}
170
171static int read_config_byte(struct pci_config_swap *swap,
172 struct pci_bus *bus, u32 devfn, u32 where,
173 u8 * val)
174{
175 int status;
176 u32 result;
177
178 status = read_config_dword(swap, bus, devfn, where & ~3, &result);
179 if (where & 1)
180 result >>= 8;
181 if (where & 2)
182 result >>= 16;
183 *val = result & 0xff;
184
185 return status;
186}
187
188static int write_config_dword(struct pci_config_swap *swap,
189 struct pci_bus *bus, u32 devfn, u32 where,
190 u32 val)
191{
192 u32 bus_num, slot_num, func_num;
193 u32 base;
194
195 db_assert((where & 3) == 0);
196 db_assert(where < (1 << 8));
197
198 /* check if the bus is top-level */
199 if (bus->parent != NULL) {
200 bus_num = bus->number;
201 db_assert(bus_num != 0);
202 } else {
203 bus_num = 0;
204 }
205
206 slot_num = PCI_SLOT(devfn);
207 func_num = PCI_FUNC(devfn);
208 base = ddb_access_config_base(swap, bus_num, slot_num);
209 *(volatile u32 *) (base + (func_num << 8) + where) = val;
210 ddb_close_config_base(swap);
211 return PCIBIOS_SUCCESSFUL;
212}
213
214static int write_config_word(struct pci_config_swap *swap,
215 struct pci_bus *bus, u32 devfn, u32 where, u16 val)
216{
217 int status, shift = 0;
218 u32 result;
219
220 db_assert((where & 1) == 0);
221
222 status = read_config_dword(swap, bus, devfn, where & ~3, &result);
223 if (status != PCIBIOS_SUCCESSFUL)
224 return status;
225
226 if (where & 2)
227 shift += 16;
228 result &= ~(0xffff << shift);
229 result |= val << shift;
230 return write_config_dword(swap, bus, devfn, where & ~3, result);
231}
232
233static int write_config_byte(struct pci_config_swap *swap,
234 struct pci_bus *bus, u32 devfn, u32 where, u8 val)
235{
236 int status, shift = 0;
237 u32 result;
238
239 status = read_config_dword(swap, bus, devfn, where & ~3, &result);
240 if (status != PCIBIOS_SUCCESSFUL)
241 return status;
242
243 if (where & 2)
244 shift += 16;
245 if (where & 1)
246 shift += 8;
247 result &= ~(0xff << shift);
248 result |= val << shift;
249 return write_config_dword(swap, bus, devfn, where & ~3, result);
250}
251
252#define MAKE_PCI_OPS(prefix, rw, pciswap, star) \
253static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \
254{ \
255 if (size == 1) \
256 return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \
257 else if (size == 2) \
258 return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \
259 /* Size must be 4 */ \
260 return rw##_config_dword(pciswap, bus, devfn, where, val); \
261}
262
263MAKE_PCI_OPS(extpci, read, &ext_pci_swap, *)
264MAKE_PCI_OPS(extpci, write, &ext_pci_swap,)
265
266MAKE_PCI_OPS(iopci, read, &io_pci_swap, *)
267MAKE_PCI_OPS(iopci, write, &io_pci_swap,)
268
269struct pci_ops ddb5477_ext_pci_ops = {
270 .read = extpci_read_config,
271 .write = extpci_write_config
272};
273
274
275struct pci_ops ddb5477_io_pci_ops = {
276 .read = iopci_read_config,
277 .write = iopci_write_config
278};
diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c
index 38f181625e10..d31bfc6d4150 100644
--- a/arch/mips/pci/ops-emma2rh.c
+++ b/arch/mips/pci/ops-emma2rh.c
@@ -45,7 +45,7 @@ static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num)
45 /* check if the bus is top-level */ 45 /* check if the bus is top-level */
46 if (bus->parent != NULL) { 46 if (bus->parent != NULL) {
47 *bus_num = bus->number; 47 *bus_num = bus->number;
48 db_assert(bus_num != 0); 48 db_assert(bus_num != NULL);
49 } else 49 } else
50 *bus_num = 0; 50 *bus_num = 0;
51 51
diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c
index f556b7a8dccd..d61064652498 100644
--- a/arch/mips/pci/ops-pnx8550.c
+++ b/arch/mips/pci/ops-pnx8550.c
@@ -117,7 +117,7 @@ read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
117 unsigned int data = 0; 117 unsigned int data = 0;
118 int err; 118 int err;
119 119
120 if (bus == 0) 120 if (bus == NULL)
121 return -1; 121 return -1;
122 122
123 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); 123 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
@@ -145,7 +145,7 @@ read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
145 unsigned int data = 0; 145 unsigned int data = 0;
146 int err; 146 int err;
147 147
148 if (bus == 0) 148 if (bus == NULL)
149 return -1; 149 return -1;
150 150
151 if (where & 0x01) 151 if (where & 0x01)
@@ -168,7 +168,7 @@ static int
168read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val) 168read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
169{ 169{
170 int err; 170 int err;
171 if (bus == 0) 171 if (bus == NULL)
172 return -1; 172 return -1;
173 173
174 if (where & 0x03) 174 if (where & 0x03)
@@ -185,7 +185,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
185 unsigned int data = (unsigned int)val; 185 unsigned int data = (unsigned int)val;
186 int err; 186 int err;
187 187
188 if (bus == 0) 188 if (bus == NULL)
189 return -1; 189 return -1;
190 190
191 switch (where & 0x03) { 191 switch (where & 0x03) {
@@ -213,7 +213,7 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
213 unsigned int data = (unsigned int)val; 213 unsigned int data = (unsigned int)val;
214 int err; 214 int err;
215 215
216 if (bus == 0) 216 if (bus == NULL)
217 return -1; 217 return -1;
218 218
219 if (where & 0x01) 219 if (where & 0x01)
@@ -235,7 +235,7 @@ static int
235write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) 235write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
236{ 236{
237 int err; 237 int err;
238 if (bus == 0) 238 if (bus == NULL)
239 return -1; 239 return -1;
240 240
241 if (where & 0x03) 241 if (where & 0x03)
diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c
deleted file mode 100644
index 7363e1877842..000000000000
--- a/arch/mips/pci/pci-ddb5477.c
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * PCI code for DDB5477.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/pci.h>
18
19#include <asm/bootinfo.h>
20#include <asm/debug.h>
21
22#include <asm/ddb5xxx/ddb5xxx.h>
23
24static struct resource extpci_io_resource = {
25 .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
26 .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
27 .name = "ext pci IO space",
28 .flags = IORESOURCE_IO
29};
30
31static struct resource extpci_mem_resource = {
32 .start = DDB_PCI0_MEM_BASE + 0x100000,
33 .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
34 .name = "ext pci memory space",
35 .flags = IORESOURCE_MEM
36};
37
38static struct resource iopci_io_resource = {
39 .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
40 .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
41 .name = "io pci IO space",
42 .flags = IORESOURCE_IO
43};
44
45static struct resource iopci_mem_resource = {
46 .start = DDB_PCI1_MEM_BASE,
47 .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
48 .name = "ext pci memory space",
49 .flags = IORESOURCE_MEM
50};
51
52extern struct pci_ops ddb5477_ext_pci_ops;
53extern struct pci_ops ddb5477_io_pci_ops;
54
55struct pci_controller ddb5477_ext_controller = {
56 .pci_ops = &ddb5477_ext_pci_ops,
57 .io_resource = &extpci_io_resource,
58 .mem_resource = &extpci_mem_resource
59};
60
61struct pci_controller ddb5477_io_controller = {
62 .pci_ops = &ddb5477_io_pci_ops,
63 .io_resource = &iopci_io_resource,
64 .mem_resource = &iopci_mem_resource
65};
66
67
68
69/*
70 * we fix up irqs based on the slot number.
71 * The first entry is at AD:11.
72 * Fortunately this works because, although we have two pci buses,
73 * they all have different slot numbers (except for rockhopper slot 20
74 * which is handled below).
75 *
76 */
77
78/*
79 * irq mapping : device -> pci int # -> vrc4377 irq# ,
80 * ddb5477 board manual page 4 and vrc5477 manual page 46
81 */
82
83/*
84 * based on ddb5477 manual page 11
85 */
86#define MAX_SLOT_NUM 21
87static unsigned char irq_map[MAX_SLOT_NUM] = {
88 /* SLOT: 0, AD:11 */ 0xff,
89 /* SLOT: 1, AD:12 */ 0xff,
90 /* SLOT: 2, AD:13 */ 0xff,
91 /* SLOT: 3, AD:14 */ 0xff,
92 /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */
93 /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */
94 /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */
95 /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */
96 /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */
97 /* SLOT: 9, AD:20 */ 0xff,
98 /* SLOT: 10, AD:21 */ 0xff,
99 /* SLOT: 11, AD:22 */ 0xff,
100 /* SLOT: 12, AD:23 */ 0xff,
101 /* SLOT: 13, AD:24 */ 0xff,
102 /* SLOT: 14, AD:25 */ 0xff,
103 /* SLOT: 15, AD:26 */ 0xff,
104 /* SLOT: 16, AD:27 */ 0xff,
105 /* SLOT: 17, AD:28 */ 0xff,
106 /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
107 /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
108 /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
109};
110static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
111 /* SLOT: 0, AD:11 */ 0xff,
112 /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */
113 /* SLOT: 2, AD:13 */ 0xff,
114 /* SLOT: 3, AD:14 */ 0xff,
115 /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */
116 /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */
117 /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */
118 /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */
119 /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */
120 /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */
121 /* SLOT: 10, AD:21 */ 0xff,
122 /* SLOT: 11, AD:22 */ 0xff,
123 /* SLOT: 12, AD:23 */ 0xff,
124 /* SLOT: 13, AD:24 */ 0xff,
125 /* SLOT: 14, AD:25 */ 0xff,
126 /* SLOT: 15, AD:26 */ 0xff,
127 /* SLOT: 16, AD:27 */ 0xff,
128 /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */
129 /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
130 /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
131 /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
132};
133
134int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
135{
136 int slot_num;
137 unsigned char *slot_irq_map;
138 unsigned char irq;
139
140 /*
141 * We ignore the swizzled slot and pin values. The original
142 * pci_fixup_irq() codes largely base irq number on the dev slot
143 * numbers because except for one case they are unique even
144 * though there are multiple pci buses.
145 */
146
147 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
148 slot_irq_map = rockhopperII_irq_map;
149 else
150 slot_irq_map = irq_map;
151
152 slot_num = PCI_SLOT(dev->devfn);
153 irq = slot_irq_map[slot_num];
154
155 db_assert(slot_num < MAX_SLOT_NUM);
156
157 db_assert(irq != 0xff);
158
159 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
160
161 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
162 /* hack to distinquish overlapping slot 20s, one
163 * on bus 0 (ALI USB on the M1535 on the backplane),
164 * and one on bus 2 (NEC USB controller on the CPU board)
165 * Make the M1535 USB - ISA IRQ number 9.
166 */
167 if (slot_num == 20 && dev->bus->number == 0) {
168 pci_write_config_byte(dev,
169 PCI_INTERRUPT_LINE,
170 9);
171 irq = 9;
172 }
173
174 }
175
176 return irq;
177}
178
179/* Do platform specific device initialization at pci_enable_device() time */
180int pcibios_plat_dev_init(struct pci_dev *dev)
181{
182 return 0;
183}
184
185void ddb_pci_reset_bus(void)
186{
187 u32 temp;
188
189 /*
190 * I am not sure about the "official" procedure, the following
191 * steps work as far as I know:
192 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
193 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
194 * The same is true for both PCI channels.
195 */
196 temp = ddb_in32(DDB_PCICTL0_H);
197 temp |= 0x80000000;
198 ddb_out32(DDB_PCICTL0_H, temp);
199 temp &= ~0xc0000000;
200 ddb_out32(DDB_PCICTL0_H, temp);
201
202 temp = ddb_in32(DDB_PCICTL1_H);
203 temp |= 0x80000000;
204 ddb_out32(DDB_PCICTL1_H, temp);
205 temp &= ~0xc0000000;
206 ddb_out32(DDB_PCICTL1_H, temp);
207}
diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c
deleted file mode 100644
index 1421d34535ef..000000000000
--- a/arch/mips/pci/pci-ocelot.c
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Galileo Evaluation Boards PCI support.
4 *
5 * The general-purpose functions to read/write and configure the GT64120A's
6 * PCI registers (function names start with pci0 or pci1) are either direct
7 * copies of functions written by Galileo Technology, or are modifications
8 * of their functions to work with Linux 2.4 vs Linux 2.2. These functions
9 * are Copyright - Galileo Technology.
10 *
11 * Other functions are derived from other MIPS PCI implementations, or were
12 * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 *
15 * Copyright 2001 MontaVista Software Inc.
16 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38#include <linux/init.h>
39#include <linux/types.h>
40#include <linux/pci.h>
41#include <linux/kernel.h>
42#include <linux/slab.h>
43#include <linux/cache.h>
44#include <asm/pci.h>
45#include <asm/io.h>
46#include <asm/gt64120.h>
47
48static inline unsigned int pci0ReadConfigReg(unsigned int offset)
49{
50 unsigned int DataForRegCf8;
51 unsigned int data;
52
53 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
54 (PCI_FUNC(device->devfn) << 8) |
55 (offset & ~0x3)) | 0x80000000;
56 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
57 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
58
59 return data;
60}
61
62static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data)
63{
64 unsigned int DataForRegCf8;
65
66 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
67 (PCI_FUNC(device->devfn) << 8) |
68 (offset & ~0x3)) | 0x80000000;
69 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
70 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
71}
72
73static struct resource ocelot_mem_resource = {
74 .start = GT_PCI_MEM_BASE,
75 .end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1,
76};
77
78static struct resource ocelot_io_resource = {
79 .start = GT_PCI_IO_BASE,
80 .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
81};
82
83static struct pci_controller ocelot_pci_controller = {
84 .pci_ops = gt64xxx_pci0_ops,
85 .mem_resource = &ocelot_mem_resource,
86 .io_resource = &ocelot_io_resource,
87};
88
89static int __init ocelot_pcibios_init(void)
90{
91 u32 tmp;
92
93 GT_READ(GT_PCI0_CMD_OFS, &tmp);
94 GT_READ(GT_PCI0_BARE_OFS, &tmp);
95
96 /*
97 * You have to enable bus mastering to configure any other
98 * card on the bus.
99 */
100 tmp = pci0ReadConfigReg(PCI_COMMAND);
101 tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
102 pci0WriteConfigReg(PCI_COMMAND, tmp);
103
104 register_pci_controller(&ocelot_pci_controller);
105}
106
107arch_initcall(ocelot_pcibios_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 06:02:23 -0500