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-rw-r--r--arch/mips/pci/msi-octeon.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 2b91b0e61566..ab0c5d14c6f7 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -15,6 +15,7 @@
15#include <asm/octeon/cvmx-npi-defs.h> 15#include <asm/octeon/cvmx-npi-defs.h>
16#include <asm/octeon/cvmx-pci-defs.h> 16#include <asm/octeon/cvmx-pci-defs.h>
17#include <asm/octeon/cvmx-npei-defs.h> 17#include <asm/octeon/cvmx-npei-defs.h>
18#include <asm/octeon/cvmx-sli-defs.h>
18#include <asm/octeon/cvmx-pexp-defs.h> 19#include <asm/octeon/cvmx-pexp-defs.h>
19#include <asm/octeon/pci-octeon.h> 20#include <asm/octeon/pci-octeon.h>
20 21
@@ -162,6 +163,11 @@ msi_irq_allocated:
162 msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff; 163 msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
163 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; 164 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
164 break; 165 break;
166 case OCTEON_DMA_BAR_TYPE_PCIE2:
167 /* When using PCIe2, Bar 0 is based at 0 */
168 msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
169 msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
170 break;
165 default: 171 default:
166 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type"); 172 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
167 } 173 }