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-rw-r--r--arch/mips/pci/pcie-octeon.c1372
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diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
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index 000000000000..6aa5c542d52d
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+++ b/arch/mips/pci/pcie-octeon.c
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007, 2008 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14
15#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-npei-defs.h>
17#include <asm/octeon/cvmx-pciercx-defs.h>
18#include <asm/octeon/cvmx-pescx-defs.h>
19#include <asm/octeon/cvmx-pexp-defs.h>
20#include <asm/octeon/cvmx-helper-errata.h>
21#include <asm/octeon/pci-octeon.h>
22
23union cvmx_pcie_address {
24 uint64_t u64;
25 struct {
26 uint64_t upper:2; /* Normally 2 for XKPHYS */
27 uint64_t reserved_49_61:13; /* Must be zero */
28 uint64_t io:1; /* 1 for IO space access */
29 uint64_t did:5; /* PCIe DID = 3 */
30 uint64_t subdid:3; /* PCIe SubDID = 1 */
31 uint64_t reserved_36_39:4; /* Must be zero */
32 uint64_t es:2; /* Endian swap = 1 */
33 uint64_t port:2; /* PCIe port 0,1 */
34 uint64_t reserved_29_31:3; /* Must be zero */
35 /*
36 * Selects the type of the configuration request (0 = type 0,
37 * 1 = type 1).
38 */
39 uint64_t ty:1;
40 /* Target bus number sent in the ID in the request. */
41 uint64_t bus:8;
42 /*
43 * Target device number sent in the ID in the
44 * request. Note that Dev must be zero for type 0
45 * configuration requests.
46 */
47 uint64_t dev:5;
48 /* Target function number sent in the ID in the request. */
49 uint64_t func:3;
50 /*
51 * Selects a register in the configuration space of
52 * the target.
53 */
54 uint64_t reg:12;
55 } config;
56 struct {
57 uint64_t upper:2; /* Normally 2 for XKPHYS */
58 uint64_t reserved_49_61:13; /* Must be zero */
59 uint64_t io:1; /* 1 for IO space access */
60 uint64_t did:5; /* PCIe DID = 3 */
61 uint64_t subdid:3; /* PCIe SubDID = 2 */
62 uint64_t reserved_36_39:4; /* Must be zero */
63 uint64_t es:2; /* Endian swap = 1 */
64 uint64_t port:2; /* PCIe port 0,1 */
65 uint64_t address:32; /* PCIe IO address */
66 } io;
67 struct {
68 uint64_t upper:2; /* Normally 2 for XKPHYS */
69 uint64_t reserved_49_61:13; /* Must be zero */
70 uint64_t io:1; /* 1 for IO space access */
71 uint64_t did:5; /* PCIe DID = 3 */
72 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
73 uint64_t reserved_36_39:4; /* Must be zero */
74 uint64_t address:36; /* PCIe Mem address */
75 } mem;
76};
77
78/**
79 * Return the Core virtual base address for PCIe IO access. IOs are
80 * read/written as an offset from this address.
81 *
82 * @pcie_port: PCIe port the IO is for
83 *
84 * Returns 64bit Octeon IO base address for read/write
85 */
86static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
87{
88 union cvmx_pcie_address pcie_addr;
89 pcie_addr.u64 = 0;
90 pcie_addr.io.upper = 0;
91 pcie_addr.io.io = 1;
92 pcie_addr.io.did = 3;
93 pcie_addr.io.subdid = 2;
94 pcie_addr.io.es = 1;
95 pcie_addr.io.port = pcie_port;
96 return pcie_addr.u64;
97}
98
99/**
100 * Size of the IO address region returned at address
101 * cvmx_pcie_get_io_base_address()
102 *
103 * @pcie_port: PCIe port the IO is for
104 *
105 * Returns Size of the IO window
106 */
107static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
108{
109 return 1ull << 32;
110}
111
112/**
113 * Return the Core virtual base address for PCIe MEM access. Memory is
114 * read/written as an offset from this address.
115 *
116 * @pcie_port: PCIe port the IO is for
117 *
118 * Returns 64bit Octeon IO base address for read/write
119 */
120static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
121{
122 union cvmx_pcie_address pcie_addr;
123 pcie_addr.u64 = 0;
124 pcie_addr.mem.upper = 0;
125 pcie_addr.mem.io = 1;
126 pcie_addr.mem.did = 3;
127 pcie_addr.mem.subdid = 3 + pcie_port;
128 return pcie_addr.u64;
129}
130
131/**
132 * Size of the Mem address region returned at address
133 * cvmx_pcie_get_mem_base_address()
134 *
135 * @pcie_port: PCIe port the IO is for
136 *
137 * Returns Size of the Mem window
138 */
139static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
140{
141 return 1ull << 36;
142}
143
144/**
145 * Read a PCIe config space register indirectly. This is used for
146 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
147 *
148 * @pcie_port: PCIe port to read from
149 * @cfg_offset: Address to read
150 *
151 * Returns Value read
152 */
153static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
154{
155 union cvmx_pescx_cfg_rd pescx_cfg_rd;
156 pescx_cfg_rd.u64 = 0;
157 pescx_cfg_rd.s.addr = cfg_offset;
158 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
159 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
160 return pescx_cfg_rd.s.data;
161}
162
163/**
164 * Write a PCIe config space register indirectly. This is used for
165 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
166 *
167 * @pcie_port: PCIe port to write to
168 * @cfg_offset: Address to write
169 * @val: Value to write
170 */
171static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
172 uint32_t val)
173{
174 union cvmx_pescx_cfg_wr pescx_cfg_wr;
175 pescx_cfg_wr.u64 = 0;
176 pescx_cfg_wr.s.addr = cfg_offset;
177 pescx_cfg_wr.s.data = val;
178 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
179}
180
181/**
182 * Build a PCIe config space request address for a device
183 *
184 * @pcie_port: PCIe port to access
185 * @bus: Sub bus
186 * @dev: Device ID
187 * @fn: Device sub function
188 * @reg: Register to access
189 *
190 * Returns 64bit Octeon IO address
191 */
192static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
193 int dev, int fn, int reg)
194{
195 union cvmx_pcie_address pcie_addr;
196 union cvmx_pciercx_cfg006 pciercx_cfg006;
197
198 pciercx_cfg006.u32 =
199 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
200 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
201 return 0;
202
203 pcie_addr.u64 = 0;
204 pcie_addr.config.upper = 2;
205 pcie_addr.config.io = 1;
206 pcie_addr.config.did = 3;
207 pcie_addr.config.subdid = 1;
208 pcie_addr.config.es = 1;
209 pcie_addr.config.port = pcie_port;
210 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
211 pcie_addr.config.bus = bus;
212 pcie_addr.config.dev = dev;
213 pcie_addr.config.func = fn;
214 pcie_addr.config.reg = reg;
215 return pcie_addr.u64;
216}
217
218/**
219 * Read 8bits from a Device's config space
220 *
221 * @pcie_port: PCIe port the device is on
222 * @bus: Sub bus
223 * @dev: Device ID
224 * @fn: Device sub function
225 * @reg: Register to access
226 *
227 * Returns Result of the read
228 */
229static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
230 int fn, int reg)
231{
232 uint64_t address =
233 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
234 if (address)
235 return cvmx_read64_uint8(address);
236 else
237 return 0xff;
238}
239
240/**
241 * Read 16bits from a Device's config space
242 *
243 * @pcie_port: PCIe port the device is on
244 * @bus: Sub bus
245 * @dev: Device ID
246 * @fn: Device sub function
247 * @reg: Register to access
248 *
249 * Returns Result of the read
250 */
251static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
252 int fn, int reg)
253{
254 uint64_t address =
255 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
256 if (address)
257 return le16_to_cpu(cvmx_read64_uint16(address));
258 else
259 return 0xffff;
260}
261
262/**
263 * Read 32bits from a Device's config space
264 *
265 * @pcie_port: PCIe port the device is on
266 * @bus: Sub bus
267 * @dev: Device ID
268 * @fn: Device sub function
269 * @reg: Register to access
270 *
271 * Returns Result of the read
272 */
273static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
274 int fn, int reg)
275{
276 uint64_t address =
277 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
278 if (address)
279 return le32_to_cpu(cvmx_read64_uint32(address));
280 else
281 return 0xffffffff;
282}
283
284/**
285 * Write 8bits to a Device's config space
286 *
287 * @pcie_port: PCIe port the device is on
288 * @bus: Sub bus
289 * @dev: Device ID
290 * @fn: Device sub function
291 * @reg: Register to access
292 * @val: Value to write
293 */
294static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
295 int reg, uint8_t val)
296{
297 uint64_t address =
298 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
299 if (address)
300 cvmx_write64_uint8(address, val);
301}
302
303/**
304 * Write 16bits to a Device's config space
305 *
306 * @pcie_port: PCIe port the device is on
307 * @bus: Sub bus
308 * @dev: Device ID
309 * @fn: Device sub function
310 * @reg: Register to access
311 * @val: Value to write
312 */
313static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
314 int reg, uint16_t val)
315{
316 uint64_t address =
317 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
318 if (address)
319 cvmx_write64_uint16(address, cpu_to_le16(val));
320}
321
322/**
323 * Write 32bits to a Device's config space
324 *
325 * @pcie_port: PCIe port the device is on
326 * @bus: Sub bus
327 * @dev: Device ID
328 * @fn: Device sub function
329 * @reg: Register to access
330 * @val: Value to write
331 */
332static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
333 int reg, uint32_t val)
334{
335 uint64_t address =
336 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
337 if (address)
338 cvmx_write64_uint32(address, cpu_to_le32(val));
339}
340
341/**
342 * Initialize the RC config space CSRs
343 *
344 * @pcie_port: PCIe port to initialize
345 */
346static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
347{
348 union cvmx_pciercx_cfg030 pciercx_cfg030;
349 union cvmx_npei_ctl_status2 npei_ctl_status2;
350 union cvmx_pciercx_cfg070 pciercx_cfg070;
351 union cvmx_pciercx_cfg001 pciercx_cfg001;
352 union cvmx_pciercx_cfg032 pciercx_cfg032;
353 union cvmx_pciercx_cfg006 pciercx_cfg006;
354 union cvmx_pciercx_cfg008 pciercx_cfg008;
355 union cvmx_pciercx_cfg009 pciercx_cfg009;
356 union cvmx_pciercx_cfg010 pciercx_cfg010;
357 union cvmx_pciercx_cfg011 pciercx_cfg011;
358 union cvmx_pciercx_cfg035 pciercx_cfg035;
359 union cvmx_pciercx_cfg075 pciercx_cfg075;
360 union cvmx_pciercx_cfg034 pciercx_cfg034;
361
362 /* Max Payload Size (PCIE*_CFG030[MPS]) */
363 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
364 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
365 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
366 pciercx_cfg030.u32 =
367 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
368 /*
369 * Max payload size = 128 bytes for best Octeon DMA
370 * performance.
371 */
372 pciercx_cfg030.s.mps = 0;
373 /*
374 * Max read request size = 128 bytes for best Octeon DMA
375 * performance.
376 */
377 pciercx_cfg030.s.mrrs = 0;
378 /* Enable relaxed ordering. */
379 pciercx_cfg030.s.ro_en = 1;
380 /* Enable no snoop. */
381 pciercx_cfg030.s.ns_en = 1;
382 /* Correctable error reporting enable. */
383 pciercx_cfg030.s.ce_en = 1;
384 /* Non-fatal error reporting enable. */
385 pciercx_cfg030.s.nfe_en = 1;
386 /* Fatal error reporting enable. */
387 pciercx_cfg030.s.fe_en = 1;
388 /* Unsupported request reporting enable. */
389 pciercx_cfg030.s.ur_en = 1;
390 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
391 pciercx_cfg030.u32);
392
393 /*
394 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
395 * PCIE*_CFG030[MPS]
396 *
397 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
398 * exceed PCIE*_CFG030[MRRS].
399 */
400 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
401 /* Max payload size = 128 bytes for best Octeon DMA performance */
402 npei_ctl_status2.s.mps = 0;
403 /* Max read request size = 128 bytes for best Octeon DMA performance */
404 npei_ctl_status2.s.mrrs = 0;
405 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
406
407 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
408 pciercx_cfg070.u32 =
409 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
410 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
411 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
412 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
413 pciercx_cfg070.u32);
414
415 /*
416 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
417 * always be set.
418 *
419 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
420 * Message Enable (PCIE*_CFG001[SEE])
421 */
422 pciercx_cfg001.u32 =
423 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
424 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
425 pciercx_cfg001.s.me = 1; /* Bus master enable. */
426 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
427 pciercx_cfg001.s.see = 1; /* SERR# enable */
428 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
429 pciercx_cfg001.u32);
430
431 /* Advanced Error Recovery Message Enables */
432 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
433 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
434 /* Use CVMX_PCIERCX_CFG067 hardware default */
435 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
436
437 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
438 pciercx_cfg032.u32 =
439 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
440 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
441 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
442 pciercx_cfg032.u32);
443
444 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
445
446 /*
447 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
448 * cvmx_pcie_rc_initialize_link()
449 *
450 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
451 *
452 * We set the primary bus number to 1 so IDT bridges are
453 * happy. They don't like zero.
454 */
455 pciercx_cfg006.u32 = 0;
456 pciercx_cfg006.s.pbnum = 1;
457 pciercx_cfg006.s.sbnum = 1;
458 pciercx_cfg006.s.subbnum = 1;
459 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
460 pciercx_cfg006.u32);
461
462 /*
463 * Memory-mapped I/O BAR (PCIERCn_CFG008)
464 * Most applications should disable the memory-mapped I/O BAR by
465 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
466 */
467 pciercx_cfg008.u32 = 0;
468 pciercx_cfg008.s.mb_addr = 0x100;
469 pciercx_cfg008.s.ml_addr = 0;
470 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
471 pciercx_cfg008.u32);
472
473 /*
474 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
475 * Most applications should disable the prefetchable BAR by setting
476 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
477 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
478 */
479 pciercx_cfg009.u32 =
480 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
481 pciercx_cfg010.u32 =
482 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
483 pciercx_cfg011.u32 =
484 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
485 pciercx_cfg009.s.lmem_base = 0x100;
486 pciercx_cfg009.s.lmem_limit = 0;
487 pciercx_cfg010.s.umem_base = 0x100;
488 pciercx_cfg011.s.umem_limit = 0;
489 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
490 pciercx_cfg009.u32);
491 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
492 pciercx_cfg010.u32);
493 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
494 pciercx_cfg011.u32);
495
496 /*
497 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
498 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
499 */
500 pciercx_cfg035.u32 =
501 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
502 /* System error on correctable error enable. */
503 pciercx_cfg035.s.secee = 1;
504 /* System error on fatal error enable. */
505 pciercx_cfg035.s.sefee = 1;
506 /* System error on non-fatal error enable. */
507 pciercx_cfg035.s.senfee = 1;
508 /* PME interrupt enable. */
509 pciercx_cfg035.s.pmeie = 1;
510 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
511 pciercx_cfg035.u32);
512
513 /*
514 * Advanced Error Recovery Interrupt Enables
515 * (PCIERCn_CFG075[CERE,NFERE,FERE])
516 */
517 pciercx_cfg075.u32 =
518 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
519 /* Correctable error reporting enable. */
520 pciercx_cfg075.s.cere = 1;
521 /* Non-fatal error reporting enable. */
522 pciercx_cfg075.s.nfere = 1;
523 /* Fatal error reporting enable. */
524 pciercx_cfg075.s.fere = 1;
525 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
526 pciercx_cfg075.u32);
527
528 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
529 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
530 */
531 pciercx_cfg034.u32 =
532 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
533 /* Hot-plug interrupt enable. */
534 pciercx_cfg034.s.hpint_en = 1;
535 /* Data Link Layer state changed enable */
536 pciercx_cfg034.s.dlls_en = 1;
537 /* Command completed interrupt enable. */
538 pciercx_cfg034.s.ccint_en = 1;
539 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
540 pciercx_cfg034.u32);
541}
542
543/**
544 * Initialize a host mode PCIe link. This function takes a PCIe
545 * port from reset to a link up state. Software can then begin
546 * configuring the rest of the link.
547 *
548 * @pcie_port: PCIe port to initialize
549 *
550 * Returns Zero on success
551 */
552static int __cvmx_pcie_rc_initialize_link(int pcie_port)
553{
554 uint64_t start_cycle;
555 union cvmx_pescx_ctl_status pescx_ctl_status;
556 union cvmx_pciercx_cfg452 pciercx_cfg452;
557 union cvmx_pciercx_cfg032 pciercx_cfg032;
558 union cvmx_pciercx_cfg448 pciercx_cfg448;
559
560 /* Set the lane width */
561 pciercx_cfg452.u32 =
562 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
563 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
564 if (pescx_ctl_status.s.qlm_cfg == 0) {
565 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
566 pciercx_cfg452.s.lme = 0xf;
567 } else {
568 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
569 pciercx_cfg452.s.lme = 0x7;
570 }
571 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
572 pciercx_cfg452.u32);
573
574 /*
575 * CN52XX pass 1.x has an errata where length mismatches on UR
576 * responses can cause bus errors on 64bit memory
577 * reads. Turning off length error checking fixes this.
578 */
579 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
580 union cvmx_pciercx_cfg455 pciercx_cfg455;
581 pciercx_cfg455.u32 =
582 cvmx_pcie_cfgx_read(pcie_port,
583 CVMX_PCIERCX_CFG455(pcie_port));
584 pciercx_cfg455.s.m_cpl_len_err = 1;
585 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
586 pciercx_cfg455.u32);
587 }
588
589 /* Lane swap needs to be manually enabled for CN52XX */
590 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
591 pescx_ctl_status.s.lane_swp = 1;
592 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
593 pescx_ctl_status.u64);
594 }
595
596 /* Bring up the link */
597 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
598 pescx_ctl_status.s.lnk_enb = 1;
599 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
600
601 /*
602 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
603 * be disabled.
604 */
605 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
606 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
607
608 /* Wait for the link to come up */
609 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
610 start_cycle = cvmx_get_cycle();
611 do {
612 if (cvmx_get_cycle() - start_cycle >
613 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
614 cvmx_dprintf("PCIe: Port %d link timeout\n",
615 pcie_port);
616 return -1;
617 }
618 cvmx_wait(10000);
619 pciercx_cfg032.u32 =
620 cvmx_pcie_cfgx_read(pcie_port,
621 CVMX_PCIERCX_CFG032(pcie_port));
622 } while (pciercx_cfg032.s.dlla == 0);
623
624 /* Display the link status */
625 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
626 pciercx_cfg032.s.nlw);
627
628 /*
629 * Update the Replay Time Limit. Empirically, some PCIe
630 * devices take a little longer to respond than expected under
631 * load. As a workaround for this we configure the Replay Time
632 * Limit to the value expected for a 512 byte MPS instead of
633 * our actual 256 byte MPS. The numbers below are directly
634 * from the PCIe spec table 3-4.
635 */
636 pciercx_cfg448.u32 =
637 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
638 switch (pciercx_cfg032.s.nlw) {
639 case 1: /* 1 lane */
640 pciercx_cfg448.s.rtl = 1677;
641 break;
642 case 2: /* 2 lanes */
643 pciercx_cfg448.s.rtl = 867;
644 break;
645 case 4: /* 4 lanes */
646 pciercx_cfg448.s.rtl = 462;
647 break;
648 case 8: /* 8 lanes */
649 pciercx_cfg448.s.rtl = 258;
650 break;
651 }
652 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
653 pciercx_cfg448.u32);
654
655 return 0;
656}
657
658/**
659 * Initialize a PCIe port for use in host(RC) mode. It doesn't
660 * enumerate the bus.
661 *
662 * @pcie_port: PCIe port to initialize
663 *
664 * Returns Zero on success
665 */
666static int cvmx_pcie_rc_initialize(int pcie_port)
667{
668 int i;
669 union cvmx_ciu_soft_prst ciu_soft_prst;
670 union cvmx_pescx_bist_status pescx_bist_status;
671 union cvmx_pescx_bist_status2 pescx_bist_status2;
672 union cvmx_npei_ctl_status npei_ctl_status;
673 union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
674 union cvmx_npei_mem_access_subidx mem_access_subid;
675 union cvmx_npei_dbg_data npei_dbg_data;
676 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
677
678 /*
679 * Make sure we aren't trying to setup a target mode interface
680 * in host mode.
681 */
682 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
683 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
684 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
685 "on port0, but port0 is not in host mode\n");
686 return -1;
687 }
688
689 /*
690 * Make sure a CN52XX isn't trying to bring up port 1 when it
691 * is disabled.
692 */
693 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
694 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
695 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
696 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
697 "called on port1, but port1 is "
698 "disabled\n");
699 return -1;
700 }
701 }
702
703 /*
704 * PCIe switch arbitration mode. '0' == fixed priority NPEI,
705 * PCIe0, then PCIe1. '1' == round robin.
706 */
707 npei_ctl_status.s.arb = 1;
708 /* Allow up to 0x20 config retries */
709 npei_ctl_status.s.cfg_rtry = 0x20;
710 /*
711 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
712 * don't reset.
713 */
714 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
715 npei_ctl_status.s.p0_ntags = 0x20;
716 npei_ctl_status.s.p1_ntags = 0x20;
717 }
718 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
719
720 /* Bring the PCIe out of reset */
721 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
722 /*
723 * The EBH5200 board swapped the PCIe reset lines on
724 * the board. As a workaround for this bug, we bring
725 * both PCIe ports out of reset at the same time
726 * instead of on separate calls. So for port 0, we
727 * bring both out of reset and do nothing on port 1.
728 */
729 if (pcie_port == 0) {
730 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
731 /*
732 * After a chip reset the PCIe will also be in
733 * reset. If it isn't, most likely someone is
734 * trying to init it again without a proper
735 * PCIe reset.
736 */
737 if (ciu_soft_prst.s.soft_prst == 0) {
738 /* Reset the ports */
739 ciu_soft_prst.s.soft_prst = 1;
740 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
741 ciu_soft_prst.u64);
742 ciu_soft_prst.u64 =
743 cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
744 ciu_soft_prst.s.soft_prst = 1;
745 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
746 ciu_soft_prst.u64);
747 /* Wait until pcie resets the ports. */
748 udelay(2000);
749 }
750 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
751 ciu_soft_prst.s.soft_prst = 0;
752 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
753 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
754 ciu_soft_prst.s.soft_prst = 0;
755 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
756 }
757 } else {
758 /*
759 * The normal case: The PCIe ports are completely
760 * separate and can be brought out of reset
761 * independently.
762 */
763 if (pcie_port)
764 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
765 else
766 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
767 /*
768 * After a chip reset the PCIe will also be in
769 * reset. If it isn't, most likely someone is trying
770 * to init it again without a proper PCIe reset.
771 */
772 if (ciu_soft_prst.s.soft_prst == 0) {
773 /* Reset the port */
774 ciu_soft_prst.s.soft_prst = 1;
775 if (pcie_port)
776 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
777 ciu_soft_prst.u64);
778 else
779 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
780 ciu_soft_prst.u64);
781 /* Wait until pcie resets the ports. */
782 udelay(2000);
783 }
784 if (pcie_port) {
785 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
786 ciu_soft_prst.s.soft_prst = 0;
787 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
788 } else {
789 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
790 ciu_soft_prst.s.soft_prst = 0;
791 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
792 }
793 }
794
795 /*
796 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
797 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
798 * fixed number of cycles.
799 */
800 cvmx_wait(400000);
801
802 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
803 CN52XX, so we only probe it on newer chips */
804 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
805 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
806 /* Clear PCLK_RUN so we can check if the clock is running */
807 pescx_ctl_status2.u64 =
808 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
809 pescx_ctl_status2.s.pclk_run = 1;
810 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
811 pescx_ctl_status2.u64);
812 /*
813 * Now that we cleared PCLK_RUN, wait for it to be set
814 * again telling us the clock is running.
815 */
816 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
817 union cvmx_pescx_ctl_status2,
818 pclk_run, ==, 1, 10000)) {
819 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
820 pcie_port);
821 return -1;
822 }
823 }
824
825 /*
826 * Check and make sure PCIe came out of reset. If it doesn't
827 * the board probably hasn't wired the clocks up and the
828 * interface should be skipped.
829 */
830 pescx_ctl_status2.u64 =
831 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
832 if (pescx_ctl_status2.s.pcierst) {
833 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
834 pcie_port);
835 return -1;
836 }
837
838 /*
839 * Check BIST2 status. If any bits are set skip this interface. This
840 * is an attempt to catch PCIE-813 on pass 1 parts.
841 */
842 pescx_bist_status2.u64 =
843 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
844 if (pescx_bist_status2.u64) {
845 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
846 "port isn't hooked up, skipping.\n",
847 pcie_port);
848 return -1;
849 }
850
851 /* Check BIST status */
852 pescx_bist_status.u64 =
853 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
854 if (pescx_bist_status.u64)
855 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
856 pcie_port, CAST64(pescx_bist_status.u64));
857
858 /* Initialize the config space CSRs */
859 __cvmx_pcie_rc_initialize_config_space(pcie_port);
860
861 /* Bring the link up */
862 if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
863 cvmx_dprintf
864 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
865 return -1;
866 }
867
868 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
869 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
870 /* Allow 16 words to combine */
871 npei_mem_access_ctl.s.max_word = 0;
872 /* Wait up to 127 cycles for more data */
873 npei_mem_access_ctl.s.timer = 127;
874 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
875
876 /* Setup Mem access SubDIDs */
877 mem_access_subid.u64 = 0;
878 /* Port the request is sent to. */
879 mem_access_subid.s.port = pcie_port;
880 /* Due to an errata on pass 1 chips, no merging is allowed. */
881 mem_access_subid.s.nmerge = 1;
882 /* Endian-swap for Reads. */
883 mem_access_subid.s.esr = 1;
884 /* Endian-swap for Writes. */
885 mem_access_subid.s.esw = 1;
886 /* No Snoop for Reads. */
887 mem_access_subid.s.nsr = 1;
888 /* No Snoop for Writes. */
889 mem_access_subid.s.nsw = 1;
890 /* Disable Relaxed Ordering for Reads. */
891 mem_access_subid.s.ror = 0;
892 /* Disable Relaxed Ordering for Writes. */
893 mem_access_subid.s.row = 0;
894 /* PCIe Adddress Bits <63:34>. */
895 mem_access_subid.s.ba = 0;
896
897 /*
898 * Setup mem access 12-15 for port 0, 16-19 for port 1,
899 * supplying 36 bits of address space.
900 */
901 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
902 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
903 mem_access_subid.u64);
904 /* Set each SUBID to extend the addressable range */
905 mem_access_subid.s.ba += 1;
906 }
907
908 /*
909 * Disable the peer to peer forwarding register. This must be
910 * setup by the OS after it enumerates the bus and assigns
911 * addresses to the PCIe busses.
912 */
913 for (i = 0; i < 4; i++) {
914 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
915 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
916 }
917
918 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
919 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
920
921 /*
922 * Disable Octeon's BAR1. It isn't needed in RC mode since
923 * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
924 * the 2nd 256MB of memory.
925 */
926 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
927
928 /*
929 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
930 * precedence where they overlap. It also overlaps with the
931 * device addresses, so make sure the peer to peer forwarding
932 * is set right.
933 */
934 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
935
936 /*
937 * Setup BAR2 attributes
938 *
939 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
940 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
941 * - WAIT_COM=0 will likely work for all applications.
942 *
943 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
944 */
945 if (pcie_port) {
946 union cvmx_npei_ctl_port1 npei_ctl_port;
947 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
948 npei_ctl_port.s.bar2_enb = 1;
949 npei_ctl_port.s.bar2_esx = 1;
950 npei_ctl_port.s.bar2_cax = 0;
951 npei_ctl_port.s.ptlp_ro = 1;
952 npei_ctl_port.s.ctlp_ro = 1;
953 npei_ctl_port.s.wait_com = 0;
954 npei_ctl_port.s.waitl_com = 0;
955 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
956 } else {
957 union cvmx_npei_ctl_port0 npei_ctl_port;
958 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
959 npei_ctl_port.s.bar2_enb = 1;
960 npei_ctl_port.s.bar2_esx = 1;
961 npei_ctl_port.s.bar2_cax = 0;
962 npei_ctl_port.s.ptlp_ro = 1;
963 npei_ctl_port.s.ctlp_ro = 1;
964 npei_ctl_port.s.wait_com = 0;
965 npei_ctl_port.s.waitl_com = 0;
966 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
967 }
968 return 0;
969}
970
971
972/* Above was cvmx-pcie.c, below original pcie.c */
973
974
975/**
976 * Map a PCI device to the appropriate interrupt line
977 *
978 * @dev: The Linux PCI device structure for the device to map
979 * @slot: The slot number for this device on __BUS 0__. Linux
980 * enumerates through all the bridges and figures out the
981 * slot on Bus 0 where this device eventually hooks to.
982 * @pin: The PCI interrupt pin read from the device, then swizzled
983 * as it goes through each bridge.
984 * Returns Interrupt number for the device
985 */
986int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
987 u8 slot, u8 pin)
988{
989 /*
990 * The EBH5600 board with the PCI to PCIe bridge mistakenly
991 * wires the first slot for both device id 2 and interrupt
992 * A. According to the PCI spec, device id 2 should be C. The
993 * following kludge attempts to fix this.
994 */
995 if (strstr(octeon_board_type_string(), "EBH5600") &&
996 dev->bus && dev->bus->parent) {
997 /*
998 * Iterate all the way up the device chain and find
999 * the root bus.
1000 */
1001 while (dev->bus && dev->bus->parent)
1002 dev = to_pci_dev(dev->bus->bridge);
1003 /* If the root bus is number 0 and the PEX 8114 is the
1004 * root, assume we are behind the miswired bus. We
1005 * need to correct the swizzle level by two. Yuck.
1006 */
1007 if ((dev->bus->number == 0) &&
1008 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1009 /*
1010 * The pin field is one based, not zero. We
1011 * need to swizzle it by minus two.
1012 */
1013 pin = ((pin - 3) & 3) + 1;
1014 }
1015 }
1016 /*
1017 * The -1 is because pin starts with one, not zero. It might
1018 * be that this equation needs to include the slot number, but
1019 * I don't have hardware to check that against.
1020 */
1021 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1022}
1023
1024/**
1025 * Read a value from configuration space
1026 *
1027 * @bus:
1028 * @devfn:
1029 * @reg:
1030 * @size:
1031 * @val:
1032 * Returns
1033 */
1034static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1035 unsigned int devfn, int reg, int size,
1036 u32 *val)
1037{
1038 union octeon_cvmemctl cvmmemctl;
1039 union octeon_cvmemctl cvmmemctl_save;
1040 int bus_number = bus->number;
1041
1042 /*
1043 * For the top level bus make sure our hardware bus number
1044 * matches the software one.
1045 */
1046 if (bus->parent == NULL) {
1047 union cvmx_pciercx_cfg006 pciercx_cfg006;
1048 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
1049 CVMX_PCIERCX_CFG006(pcie_port));
1050 if (pciercx_cfg006.s.pbnum != bus_number) {
1051 pciercx_cfg006.s.pbnum = bus_number;
1052 pciercx_cfg006.s.sbnum = bus_number;
1053 pciercx_cfg006.s.subbnum = bus_number;
1054 cvmx_pcie_cfgx_write(pcie_port,
1055 CVMX_PCIERCX_CFG006(pcie_port),
1056 pciercx_cfg006.u32);
1057 }
1058 }
1059
1060 /*
1061 * PCIe only has a single device connected to Octeon. It is
1062 * always device ID 0. Don't bother doing reads for other
1063 * device IDs on the first segment.
1064 */
1065 if ((bus->parent == NULL) && (devfn >> 3 != 0))
1066 return PCIBIOS_FUNC_NOT_SUPPORTED;
1067
1068 /*
1069 * The following is a workaround for the CN57XX, CN56XX,
1070 * CN55XX, and CN54XX errata with PCIe config reads from non
1071 * existent devices. These chips will hang the PCIe link if a
1072 * config read is performed that causes a UR response.
1073 */
1074 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1075 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
1076 /*
1077 * For our EBH5600 board, port 0 has a bridge with two
1078 * PCI-X slots. We need a new special checks to make
1079 * sure we only probe valid stuff. The PCIe->PCI-X
1080 * bridge only respondes to device ID 0, function
1081 * 0-1
1082 */
1083 if ((bus->parent == NULL) && (devfn >= 2))
1084 return PCIBIOS_FUNC_NOT_SUPPORTED;
1085 /*
1086 * The PCI-X slots are device ID 2,3. Choose one of
1087 * the below "if" blocks based on what is plugged into
1088 * the board.
1089 */
1090#if 1
1091 /* Use this option if you aren't using either slot */
1092 if (bus_number == 1)
1093 return PCIBIOS_FUNC_NOT_SUPPORTED;
1094#elif 0
1095 /*
1096 * Use this option if you are using the first slot but
1097 * not the second.
1098 */
1099 if ((bus_number == 1) && (devfn >> 3 != 2))
1100 return PCIBIOS_FUNC_NOT_SUPPORTED;
1101#elif 0
1102 /*
1103 * Use this option if you are using the second slot
1104 * but not the first.
1105 */
1106 if ((bus_number == 1) && (devfn >> 3 != 3))
1107 return PCIBIOS_FUNC_NOT_SUPPORTED;
1108#elif 0
1109 /* Use this opion if you are using both slots */
1110 if ((bus_number == 1) &&
1111 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1112 return PCIBIOS_FUNC_NOT_SUPPORTED;
1113#endif
1114
1115 /*
1116 * Shorten the DID timeout so bus errors for PCIe
1117 * config reads from non existent devices happen
1118 * faster. This allows us to continue booting even if
1119 * the above "if" checks are wrong. Once one of these
1120 * errors happens, the PCIe port is dead.
1121 */
1122 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
1123 cvmmemctl.u64 = cvmmemctl_save.u64;
1124 cvmmemctl.s.didtto = 2;
1125 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1126 }
1127
1128 switch (size) {
1129 case 4:
1130 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1131 devfn >> 3, devfn & 0x7, reg);
1132 break;
1133 case 2:
1134 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1135 devfn >> 3, devfn & 0x7, reg);
1136 break;
1137 case 1:
1138 *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
1139 devfn & 0x7, reg);
1140 break;
1141 default:
1142 return PCIBIOS_FUNC_NOT_SUPPORTED;
1143 }
1144
1145 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1146 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1147 __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
1148 return PCIBIOS_SUCCESSFUL;
1149}
1150
1151static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
1152 int reg, int size, u32 *val)
1153{
1154 return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
1155}
1156
1157static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1158 int reg, int size, u32 *val)
1159{
1160 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1161}
1162
1163
1164
1165/**
1166 * Write a value to PCI configuration space
1167 *
1168 * @bus:
1169 * @devfn:
1170 * @reg:
1171 * @size:
1172 * @val:
1173 * Returns
1174 */
1175static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
1176 unsigned int devfn, int reg,
1177 int size, u32 val)
1178{
1179 int bus_number = bus->number;
1180
1181 switch (size) {
1182 case 4:
1183 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1184 devfn & 0x7, reg, val);
1185 return PCIBIOS_SUCCESSFUL;
1186 case 2:
1187 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1188 devfn & 0x7, reg, val);
1189 return PCIBIOS_SUCCESSFUL;
1190 case 1:
1191 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1192 devfn & 0x7, reg, val);
1193 return PCIBIOS_SUCCESSFUL;
1194 }
1195#if PCI_CONFIG_SPACE_DELAY
1196 udelay(PCI_CONFIG_SPACE_DELAY);
1197#endif
1198 return PCIBIOS_FUNC_NOT_SUPPORTED;
1199}
1200
1201static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
1202 int reg, int size, u32 val)
1203{
1204 return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
1205}
1206
1207static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1208 int reg, int size, u32 val)
1209{
1210 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1211}
1212
1213static struct pci_ops octeon_pcie0_ops = {
1214 octeon_pcie0_read_config,
1215 octeon_pcie0_write_config,
1216};
1217
1218static struct resource octeon_pcie0_mem_resource = {
1219 .name = "Octeon PCIe0 MEM",
1220 .flags = IORESOURCE_MEM,
1221};
1222
1223static struct resource octeon_pcie0_io_resource = {
1224 .name = "Octeon PCIe0 IO",
1225 .flags = IORESOURCE_IO,
1226};
1227
1228static struct pci_controller octeon_pcie0_controller = {
1229 .pci_ops = &octeon_pcie0_ops,
1230 .mem_resource = &octeon_pcie0_mem_resource,
1231 .io_resource = &octeon_pcie0_io_resource,
1232};
1233
1234static struct pci_ops octeon_pcie1_ops = {
1235 octeon_pcie1_read_config,
1236 octeon_pcie1_write_config,
1237};
1238
1239static struct resource octeon_pcie1_mem_resource = {
1240 .name = "Octeon PCIe1 MEM",
1241 .flags = IORESOURCE_MEM,
1242};
1243
1244static struct resource octeon_pcie1_io_resource = {
1245 .name = "Octeon PCIe1 IO",
1246 .flags = IORESOURCE_IO,
1247};
1248
1249static struct pci_controller octeon_pcie1_controller = {
1250 .pci_ops = &octeon_pcie1_ops,
1251 .mem_resource = &octeon_pcie1_mem_resource,
1252 .io_resource = &octeon_pcie1_io_resource,
1253};
1254
1255
1256/**
1257 * Initialize the Octeon PCIe controllers
1258 *
1259 * Returns
1260 */
1261static int __init octeon_pcie_setup(void)
1262{
1263 union cvmx_npei_ctl_status npei_ctl_status;
1264 int result;
1265
1266 /* These chips don't have PCIe */
1267 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1268 return 0;
1269
1270 /* Point pcibios_map_irq() to the PCIe version of it */
1271 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1272
1273 /* Use the PCIe based DMA mappings */
1274 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1275
1276 /*
1277 * PCIe I/O range. It is based on port 0 but includes up until
1278 * port 1's end.
1279 */
1280 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1281 ioport_resource.start = 0;
1282 ioport_resource.end =
1283 cvmx_pcie_get_io_base_address(1) -
1284 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1285
1286 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1287 if (npei_ctl_status.s.host_mode) {
1288 pr_notice("PCIe: Initializing port 0\n");
1289 result = cvmx_pcie_rc_initialize(0);
1290 if (result == 0) {
1291 /* Memory offsets are physical addresses */
1292 octeon_pcie0_controller.mem_offset =
1293 cvmx_pcie_get_mem_base_address(0);
1294 /* IO offsets are Mips virtual addresses */
1295 octeon_pcie0_controller.io_map_base =
1296 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1297 (0));
1298 octeon_pcie0_controller.io_offset = 0;
1299 /*
1300 * To keep things similar to PCI, we start
1301 * device addresses at the same place as PCI
1302 * uisng big bar support. This normally
1303 * translates to 4GB-256MB, which is the same
1304 * as most x86 PCs.
1305 */
1306 octeon_pcie0_controller.mem_resource->start =
1307 cvmx_pcie_get_mem_base_address(0) +
1308 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1309 octeon_pcie0_controller.mem_resource->end =
1310 cvmx_pcie_get_mem_base_address(0) +
1311 cvmx_pcie_get_mem_size(0) - 1;
1312 /*
1313 * Ports must be above 16KB for the ISA bus
1314 * filtering in the PCI-X to PCI bridge.
1315 */
1316 octeon_pcie0_controller.io_resource->start = 4 << 10;
1317 octeon_pcie0_controller.io_resource->end =
1318 cvmx_pcie_get_io_size(0) - 1;
1319 register_pci_controller(&octeon_pcie0_controller);
1320 }
1321 } else {
1322 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1323 }
1324
1325 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1326 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1327 union cvmx_npei_dbg_data npei_dbg_data;
1328 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1329 if (npei_dbg_data.cn52xx.qlm0_link_width)
1330 return 0;
1331 }
1332
1333 pr_notice("PCIe: Initializing port 1\n");
1334 result = cvmx_pcie_rc_initialize(1);
1335 if (result == 0) {
1336 /* Memory offsets are physical addresses */
1337 octeon_pcie1_controller.mem_offset =
1338 cvmx_pcie_get_mem_base_address(1);
1339 /* IO offsets are Mips virtual addresses */
1340 octeon_pcie1_controller.io_map_base =
1341 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
1342 octeon_pcie1_controller.io_offset =
1343 cvmx_pcie_get_io_base_address(1) -
1344 cvmx_pcie_get_io_base_address(0);
1345 /*
1346 * To keep things similar to PCI, we start device
1347 * addresses at the same place as PCI uisng big bar
1348 * support. This normally translates to 4GB-256MB,
1349 * which is the same as most x86 PCs.
1350 */
1351 octeon_pcie1_controller.mem_resource->start =
1352 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
1353 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1354 octeon_pcie1_controller.mem_resource->end =
1355 cvmx_pcie_get_mem_base_address(1) +
1356 cvmx_pcie_get_mem_size(1) - 1;
1357 /*
1358 * Ports must be above 16KB for the ISA bus filtering
1359 * in the PCI-X to PCI bridge.
1360 */
1361 octeon_pcie1_controller.io_resource->start =
1362 cvmx_pcie_get_io_base_address(1) -
1363 cvmx_pcie_get_io_base_address(0);
1364 octeon_pcie1_controller.io_resource->end =
1365 octeon_pcie1_controller.io_resource->start +
1366 cvmx_pcie_get_io_size(1) - 1;
1367 register_pci_controller(&octeon_pcie1_controller);
1368 }
1369 return 0;
1370}
1371
1372arch_initcall(octeon_pcie_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 10:47:08 -0500