diff options
Diffstat (limited to 'arch/mips/pci/pci-ddb5074.c')
| -rw-r--r-- | arch/mips/pci/pci-ddb5074.c | 79 |
1 files changed, 0 insertions, 79 deletions
diff --git a/arch/mips/pci/pci-ddb5074.c b/arch/mips/pci/pci-ddb5074.c deleted file mode 100644 index 73f9ceeb2f55..000000000000 --- a/arch/mips/pci/pci-ddb5074.c +++ /dev/null | |||
| @@ -1,79 +0,0 @@ | |||
| 1 | #include <linux/kernel.h> | ||
| 2 | #include <linux/init.h> | ||
| 3 | #include <linux/types.h> | ||
| 4 | #include <linux/pci.h> | ||
| 5 | |||
| 6 | #include <asm/debug.h> | ||
| 7 | |||
| 8 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 9 | |||
| 10 | static struct resource extpci_io_resource = { | ||
| 11 | "pci IO space", | ||
| 12 | 0x1000, /* leave some room for ISA bus */ | ||
| 13 | DDB_PCI_IO_SIZE - 1, | ||
| 14 | IORESOURCE_IO | ||
| 15 | }; | ||
| 16 | |||
| 17 | static struct resource extpci_mem_resource = { | ||
| 18 | "pci memory space", | ||
| 19 | DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ | ||
| 20 | DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, | ||
| 21 | IORESOURCE_MEM | ||
| 22 | }; | ||
| 23 | |||
| 24 | extern struct pci_ops ddb5476_ext_pci_ops; | ||
| 25 | |||
| 26 | struct pci_controller ddb5476_controller = { | ||
| 27 | .pci_ops = &ddb5476_ext_pci_ops, | ||
| 28 | .io_resource = &extpci_io_resource, | ||
| 29 | .mem_resource = &extpci_mem_resource, | ||
| 30 | }; | ||
| 31 | |||
| 32 | #define PCI_EXT_INTA 8 | ||
| 33 | #define PCI_EXT_INTB 9 | ||
| 34 | #define PCI_EXT_INTC 10 | ||
| 35 | #define PCI_EXT_INTD 11 | ||
| 36 | #define PCI_EXT_INTE 12 | ||
| 37 | |||
| 38 | #define MAX_SLOT_NUM 14 | ||
| 39 | |||
| 40 | static unsigned char irq_map[MAX_SLOT_NUM] = { | ||
| 41 | [ 0] = nile4_to_irq(PCI_EXT_INTE), | ||
| 42 | [ 1] = nile4_to_irq(PCI_EXT_INTA), | ||
| 43 | [ 2] = nile4_to_irq(PCI_EXT_INTA), | ||
| 44 | [ 3] = nile4_to_irq(PCI_EXT_INTB), | ||
| 45 | [ 4] = nile4_to_irq(PCI_EXT_INTC), | ||
| 46 | [ 5] = nile4_to_irq(NILE4_INT_UART), | ||
| 47 | [10] = nile4_to_irq(PCI_EXT_INTE), | ||
| 48 | [13] = nile4_to_irq(PCI_EXT_INTE), | ||
| 49 | }; | ||
| 50 | |||
| 51 | int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | ||
| 52 | { | ||
| 53 | return irq_map[slot]; | ||
| 54 | } | ||
| 55 | |||
| 56 | /* Do platform specific device initialization at pci_enable_device() time */ | ||
| 57 | int pcibios_plat_dev_init(struct pci_dev *dev) | ||
| 58 | { | ||
| 59 | return 0; | ||
| 60 | } | ||
| 61 | |||
| 62 | void __init ddb_pci_reset_bus(void) | ||
| 63 | { | ||
| 64 | u32 temp; | ||
| 65 | |||
| 66 | /* | ||
| 67 | * I am not sure about the "official" procedure, the following | ||
| 68 | * steps work as far as I know: | ||
| 69 | * We first set PCI cold reset bit (bit 31) in PCICTRL-H. | ||
| 70 | * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. | ||
| 71 | * The same is true for both PCI channels. | ||
| 72 | */ | ||
| 73 | temp = ddb_in32(DDB_PCICTRL + 4); | ||
| 74 | temp |= 0x80000000; | ||
| 75 | ddb_out32(DDB_PCICTRL + 4, temp); | ||
| 76 | temp &= ~0xc0000000; | ||
| 77 | ddb_out32(DDB_PCICTRL + 4, temp); | ||
| 78 | |||
| 79 | } | ||