1 files changed, 217 insertions, 87 deletions

diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index c11c75be2d7e..8a0700d448fe 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -9,19 +9,13 @@
  *  by the Free Software Foundation.
  */
 
+#include <linux/spinlock.h>
 #include <linux/irq.h>
 #include <linux/pci.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
-#include <asm/mach-ath79/pci.h>
-
-#define AR724X_PCI_CFG_BASE     0x14000000
-#define AR724X_PCI_CFG_SIZE     0x1000
-#define AR724X_PCI_CTRL_BASE    (AR71XX_APB_BASE + 0x000f0000)
-#define AR724X_PCI_CTRL_SIZE    0x100
-
-#define AR724X_PCI_MEM_BASE     0x10000000
-#define AR724X_PCI_MEM_SIZE     0x04000000
 
 #define AR724X_PCI_REG_RESET            0x18
 #define AR724X_PCI_REG_INT_STATUS       0x4c
@@ -35,38 +29,112 @@
 
 #define AR7240_BAR0_WAR_VALUE   0xffff
 
-static DEFINE_SPINLOCK(ar724x_pci_lock);
-static void __iomem *ar724x_pci_devcfg_base;
-static void __iomem *ar724x_pci_ctrl_base;
+#define AR724X_PCI_CMD_INIT     (PCI_COMMAND_MEMORY |           \
+                                 PCI_COMMAND_MASTER |           \
+                                 PCI_COMMAND_INVALIDATE |       \
+                                 PCI_COMMAND_PARITY |           \
+                                 PCI_COMMAND_SERR |             \
+                                 PCI_COMMAND_FAST_BACK)
+
+struct ar724x_pci_controller {
+        void __iomem *devcfg_base;
+        void __iomem *ctrl_base;
+        void __iomem *crp_base;
+
+        int irq;
+        int irq_base;
+
+        bool link_up;
+        bool bar0_is_cached;
+        u32  bar0_value;
 
-static u32 ar724x_pci_bar0_value;
-static bool ar724x_pci_bar0_is_cached;
-static bool ar724x_pci_link_up;
+        spinlock_t lock;
 
-static inline bool ar724x_pci_check_link(void)
+        struct pci_controller pci_controller;
+        struct resource io_res;
+        struct resource mem_res;
+};
+
+static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
 {
         u32 reset;
 
-        reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
+        reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
         return reset & AR724X_PCI_RESET_LINK_UP;
 }
 
+static inline struct ar724x_pci_controller *
+pci_bus_to_ar724x_controller(struct pci_bus *bus)
+{
+        struct pci_controller *hose;
+
+        hose = (struct pci_controller *) bus->sysdata;
+        return container_of(hose, struct ar724x_pci_controller, pci_controller);
+}
+
+static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
+                                  int where, int size, u32 value)
+{
+        unsigned long flags;
+        void __iomem *base;
+        u32 data;
+        int s;
+
+        WARN_ON(where & (size - 1));
+
+        if (!apc->link_up)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        base = apc->crp_base;
+
+        spin_lock_irqsave(&apc->lock, flags);
+        data = __raw_readl(base + (where & ~3));
+
+        switch (size) {
+        case 1:
+                s = ((where & 3) * 8);
+                data &= ~(0xff << s);
+                data |= ((value & 0xff) << s);
+                break;
+        case 2:
+                s = ((where & 2) * 8);
+                data &= ~(0xffff << s);
+                data |= ((value & 0xffff) << s);
+                break;
+        case 4:
+                data = value;
+                break;
+        default:
+                spin_unlock_irqrestore(&apc->lock, flags);
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        __raw_writel(data, base + (where & ~3));
+        /* flush write */
+        __raw_readl(base + (where & ~3));
+        spin_unlock_irqrestore(&apc->lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
 static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
                             int size, uint32_t *value)
 {
+        struct ar724x_pci_controller *apc;
         unsigned long flags;
         void __iomem *base;
         u32 data;
 
-        if (!ar724x_pci_link_up)
+        apc = pci_bus_to_ar724x_controller(bus);
+        if (!apc->link_up)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         if (devfn)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
-        base = ar724x_pci_devcfg_base;
+        base = apc->devcfg_base;
 
-        spin_lock_irqsave(&ar724x_pci_lock, flags);
+        spin_lock_irqsave(&apc->lock, flags);
         data = __raw_readl(base + (where & ~3));
 
         switch (size) {
@@ -85,17 +153,17 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
         case 4:
                 break;
         default:
-                spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+                spin_unlock_irqrestore(&apc->lock, flags);
 
                 return PCIBIOS_BAD_REGISTER_NUMBER;
         }
 
-        spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+        spin_unlock_irqrestore(&apc->lock, flags);
 
         if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
-            ar724x_pci_bar0_is_cached) {
+            apc->bar0_is_cached) {
                 /* use the cached value */
-                *value = ar724x_pci_bar0_value;
+                *value = apc->bar0_value;
         } else {
                 *value = data;
         }
@@ -106,12 +174,14 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                              int size, uint32_t value)
 {
+        struct ar724x_pci_controller *apc;
         unsigned long flags;
         void __iomem *base;
         u32 data;
         int s;
 
-        if (!ar724x_pci_link_up)
+        apc = pci_bus_to_ar724x_controller(bus);
+        if (!apc->link_up)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         if (devfn)
@@ -129,18 +199,18 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                          * BAR0 register in order to make the device memory
                          * accessible.
                          */
-                        ar724x_pci_bar0_is_cached = true;
-                        ar724x_pci_bar0_value = value;
+                        apc->bar0_is_cached = true;
+                        apc->bar0_value = value;
 
                         value = AR7240_BAR0_WAR_VALUE;
                 } else {
-                        ar724x_pci_bar0_is_cached = false;
+                        apc->bar0_is_cached = false;
                 }
         }
 
-        base = ar724x_pci_devcfg_base;
+        base = apc->devcfg_base;
 
-        spin_lock_irqsave(&ar724x_pci_lock, flags);
+        spin_lock_irqsave(&apc->lock, flags);
         data = __raw_readl(base + (where & ~3));
 
         switch (size) {
@@ -158,7 +228,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                 data = value;
                 break;
         default:
-                spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+                spin_unlock_irqrestore(&apc->lock, flags);
 
                 return PCIBIOS_BAD_REGISTER_NUMBER;
         }
@@ -166,7 +236,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
         __raw_writel(data, base + (where & ~3));
         /* flush write */
         __raw_readl(base + (where & ~3));
-        spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+        spin_unlock_irqrestore(&apc->lock, flags);
 
         return PCIBIOS_SUCCESSFUL;
 }
@@ -176,38 +246,20 @@ static struct pci_ops ar724x_pci_ops = {
         .write  = ar724x_pci_write,
 };
 
-static struct resource ar724x_io_resource = {
-        .name   = "PCI IO space",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_IO,
-};
-
-static struct resource ar724x_mem_resource = {
-        .name   = "PCI memory space",
-        .start  = AR724X_PCI_MEM_BASE,
-        .end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM,
-};
-
-static struct pci_controller ar724x_pci_controller = {
-        .pci_ops        = &ar724x_pci_ops,
-        .io_resource    = &ar724x_io_resource,
-        .mem_resource   = &ar724x_mem_resource,
-};
-
 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
+        struct ar724x_pci_controller *apc;
         void __iomem *base;
         u32 pending;
 
-        base = ar724x_pci_ctrl_base;
+        apc = irq_get_handler_data(irq);
+        base = apc->ctrl_base;
 
         pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
                   __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 
         if (pending & AR724X_PCI_INT_DEV0)
-                generic_handle_irq(ATH79_PCI_IRQ(0));
+                generic_handle_irq(apc->irq_base + 0);
 
         else
                 spurious_interrupt();
@@ -215,13 +267,17 @@ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 static void ar724x_pci_irq_unmask(struct irq_data *d)
 {
+        struct ar724x_pci_controller *apc;
         void __iomem *base;
+        int offset;
         u32 t;
 
-        base = ar724x_pci_ctrl_base;
+        apc = irq_data_get_irq_chip_data(d);
+        base = apc->ctrl_base;
+        offset = apc->irq_base - d->irq;
 
-        switch (d->irq) {
-        case ATH79_PCI_IRQ(0):
+        switch (offset) {
+        case 0:
                 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
                 __raw_writel(t | AR724X_PCI_INT_DEV0,
                              base + AR724X_PCI_REG_INT_MASK);
@@ -232,13 +288,17 @@ static void ar724x_pci_irq_unmask(struct irq_data *d)
 
 static void ar724x_pci_irq_mask(struct irq_data *d)
 {
+        struct ar724x_pci_controller *apc;
         void __iomem *base;
+        int offset;
         u32 t;
 
-        base = ar724x_pci_ctrl_base;
+        apc = irq_data_get_irq_chip_data(d);
+        base = apc->ctrl_base;
+        offset = apc->irq_base - d->irq;
 
-        switch (d->irq) {
-        case ATH79_PCI_IRQ(0):
+        switch (offset) {
+        case 0:
                 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
                 __raw_writel(t & ~AR724X_PCI_INT_DEV0,
                              base + AR724X_PCI_REG_INT_MASK);
@@ -262,53 +322,123 @@ static struct irq_chip ar724x_pci_irq_chip = {
         .irq_mask_ack   = ar724x_pci_irq_mask,
 };
 
-static void __init ar724x_pci_irq_init(int irq)
+static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
+                                int id)
 {
         void __iomem *base;
         int i;
 
-        base = ar724x_pci_ctrl_base;
+        base = apc->ctrl_base;
 
         __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
         __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
 
-        BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
+        apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
 
-        for (i = ATH79_PCI_IRQ_BASE;
-             i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
+        for (i = apc->irq_base;
+             i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
                 irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
                                          handle_level_irq);
+                irq_set_chip_data(i, apc);
+        }
 
-        irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+        irq_set_handler_data(apc->irq, apc);
+        irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
 }
 
-int __init ar724x_pcibios_init(int irq)
+static int ar724x_pci_probe(struct platform_device *pdev)
 {
-        int ret;
+        struct ar724x_pci_controller *apc;
+        struct resource *res;
+        int id;
 
-        ret = -ENOMEM;
+        id = pdev->id;
+        if (id == -1)
+                id = 0;
 
-        ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
-                                         AR724X_PCI_CFG_SIZE);
-        if (ar724x_pci_devcfg_base == NULL)
-                goto err;
+        apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
+                            GFP_KERNEL);
+        if (!apc)
+                return -ENOMEM;
 
-        ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
-                                       AR724X_PCI_CTRL_SIZE);
-        if (ar724x_pci_ctrl_base == NULL)
-                goto err_unmap_devcfg;
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
+        if (!res)
+                return -EINVAL;
 
-        ar724x_pci_link_up = ar724x_pci_check_link();
-        if (!ar724x_pci_link_up)
-                pr_warn("ar724x: PCIe link is down\n");
+        apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
+        if (apc->ctrl_base == NULL)
+                return -EBUSY;
 
-        ar724x_pci_irq_init(irq);
-        register_pci_controller(&ar724x_pci_controller);
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+        if (!res)
+                return -EINVAL;
 
-        return PCIBIOS_SUCCESSFUL;
+        apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
+        if (!apc->devcfg_base)
+                return -EBUSY;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
+        if (!res)
+                return -EINVAL;
 
-err_unmap_devcfg:
-        iounmap(ar724x_pci_devcfg_base);
-err:
-        return ret;
+        apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
+        if (apc->crp_base == NULL)
+                return -EBUSY;
+
+        apc->irq = platform_get_irq(pdev, 0);
+        if (apc->irq < 0)
+                return -EINVAL;
+
+        spin_lock_init(&apc->lock);
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
+        if (!res)
+                return -EINVAL;
+
+        apc->io_res.parent = res;
+        apc->io_res.name = "PCI IO space";
+        apc->io_res.start = res->start;
+        apc->io_res.end = res->end;
+        apc->io_res.flags = IORESOURCE_IO;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
+        if (!res)
+                return -EINVAL;
+
+        apc->mem_res.parent = res;
+        apc->mem_res.name = "PCI memory space";
+        apc->mem_res.start = res->start;
+        apc->mem_res.end = res->end;
+        apc->mem_res.flags = IORESOURCE_MEM;
+
+        apc->pci_controller.pci_ops = &ar724x_pci_ops;
+        apc->pci_controller.io_resource = &apc->io_res;
+        apc->pci_controller.mem_resource = &apc->mem_res;
+
+        apc->link_up = ar724x_pci_check_link(apc);
+        if (!apc->link_up)
+                dev_warn(&pdev->dev, "PCIe link is down\n");
+
+        ar724x_pci_irq_init(apc, id);
+
+        ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
+
+        register_pci_controller(&apc->pci_controller);
+
+        return 0;
 }
+
+static struct platform_driver ar724x_pci_driver = {
+        .probe = ar724x_pci_probe,
+        .driver = {
+                .name = "ar724x-pci",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init ar724x_pci_init(void)
+{
+        return platform_driver_register(&ar724x_pci_driver);
+}
+
+postcore_initcall(ar724x_pci_init);