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path: root/arch/mips/pci/ops-gt64xxx_pci0.c
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Diffstat (limited to 'arch/mips/pci/ops-gt64xxx_pci0.c')
-rw-r--r--arch/mips/pci/ops-gt64xxx_pci0.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/mips/pci/ops-gt64xxx_pci0.c b/arch/mips/pci/ops-gt64xxx_pci0.c
index 3d896c5f413f..effcbda9f528 100644
--- a/arch/mips/pci/ops-gt64xxx_pci0.c
+++ b/arch/mips/pci/ops-gt64xxx_pci0.c
@@ -23,21 +23,21 @@
23 23
24#include <asm/gt64120.h> 24#include <asm/gt64120.h>
25 25
26#define PCI_ACCESS_READ 0 26#define PCI_ACCESS_READ 0
27#define PCI_ACCESS_WRITE 1 27#define PCI_ACCESS_WRITE 1
28 28
29/* 29/*
30 * PCI configuration cycle AD bus definition 30 * PCI configuration cycle AD bus definition
31 */ 31 */
32/* Type 0 */ 32/* Type 0 */
33#define PCI_CFG_TYPE0_REG_SHF 0 33#define PCI_CFG_TYPE0_REG_SHF 0
34#define PCI_CFG_TYPE0_FUNC_SHF 8 34#define PCI_CFG_TYPE0_FUNC_SHF 8
35 35
36/* Type 1 */ 36/* Type 1 */
37#define PCI_CFG_TYPE1_REG_SHF 0 37#define PCI_CFG_TYPE1_REG_SHF 0
38#define PCI_CFG_TYPE1_FUNC_SHF 8 38#define PCI_CFG_TYPE1_FUNC_SHF 8
39#define PCI_CFG_TYPE1_DEV_SHF 11 39#define PCI_CFG_TYPE1_DEV_SHF 11
40#define PCI_CFG_TYPE1_BUS_SHF 16 40#define PCI_CFG_TYPE1_BUS_SHF 16
41 41
42static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type, 42static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
43 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 43 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
@@ -50,7 +50,7 @@ static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
50 50
51 /* Clear cause register bits */ 51 /* Clear cause register bits */
52 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 52 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
53 GT_INTRCAUSE_TARABORT0_BIT)); 53 GT_INTRCAUSE_TARABORT0_BIT));
54 54
55 /* Setup address */ 55 /* Setup address */
56 GT_WRITE(GT_PCI0_CFGADDR_OFS, 56 GT_WRITE(GT_PCI0_CFGADDR_OFS,
@@ -87,7 +87,7 @@ static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
87 87
88 /* Clear bits */ 88 /* Clear bits */
89 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 89 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
90 GT_INTRCAUSE_TARABORT0_BIT)); 90 GT_INTRCAUSE_TARABORT0_BIT));
91 91
92 return -1; 92 return -1;
93 } 93 }
@@ -106,7 +106,7 @@ static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
106 u32 data = 0; 106 u32 data = 0;
107 107
108 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 108 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
109 where, &data)) 109 where, &data))
110 return PCIBIOS_DEVICE_NOT_FOUND; 110 return PCIBIOS_DEVICE_NOT_FOUND;
111 111
112 if (size == 1) 112 if (size == 1)
@@ -128,7 +128,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
128 data = val; 128 data = val;
129 else { 129 else {
130 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, 130 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
131 devfn, where, &data)) 131 devfn, where, &data))
132 return PCIBIOS_DEVICE_NOT_FOUND; 132 return PCIBIOS_DEVICE_NOT_FOUND;
133 133
134 if (size == 1) 134 if (size == 1)
@@ -140,7 +140,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
140 } 140 }
141 141
142 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, 142 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
143 where, &data)) 143 where, &data))
144 return PCIBIOS_DEVICE_NOT_FOUND; 144 return PCIBIOS_DEVICE_NOT_FOUND;
145 145
146 return PCIBIOS_SUCCESSFUL; 146 return PCIBIOS_SUCCESSFUL;