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-rw-r--r--arch/mips/pci/ops-au1000.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 74d91054db09..be1420126c42 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -50,11 +50,6 @@
50 50
51int (*board_pci_idsel)(unsigned int devsel, int assert); 51int (*board_pci_idsel)(unsigned int devsel, int assert);
52 52
53/* CP0 hazard avoidance. */
54#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
55 "nop; nop; nop; nop;\t" \
56 ".set reorder\n\t")
57
58void mod_wired_entry(int entry, unsigned long entrylo0, 53void mod_wired_entry(int entry, unsigned long entrylo0,
59 unsigned long entrylo1, unsigned long entryhi, 54 unsigned long entrylo1, unsigned long entryhi,
60 unsigned long pagemask) 55 unsigned long pagemask)
@@ -66,16 +61,12 @@ void mod_wired_entry(int entry, unsigned long entrylo0,
66 old_ctx = read_c0_entryhi() & 0xff; 61 old_ctx = read_c0_entryhi() & 0xff;
67 old_pagemask = read_c0_pagemask(); 62 old_pagemask = read_c0_pagemask();
68 write_c0_index(entry); 63 write_c0_index(entry);
69 BARRIER;
70 write_c0_pagemask(pagemask); 64 write_c0_pagemask(pagemask);
71 write_c0_entryhi(entryhi); 65 write_c0_entryhi(entryhi);
72 write_c0_entrylo0(entrylo0); 66 write_c0_entrylo0(entrylo0);
73 write_c0_entrylo1(entrylo1); 67 write_c0_entrylo1(entrylo1);
74 BARRIER;
75 tlb_write_indexed(); 68 tlb_write_indexed();
76 BARRIER;
77 write_c0_entryhi(old_ctx); 69 write_c0_entryhi(old_ctx);
78 BARRIER;
79 write_c0_pagemask(old_pagemask); 70 write_c0_pagemask(old_pagemask);
80} 71}
81 72