diff options
Diffstat (limited to 'arch/mips/pci/msi-octeon.c')
-rw-r--r-- | arch/mips/pci/msi-octeon.c | 277 |
1 files changed, 210 insertions, 67 deletions
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 03742e647657..d8080499872a 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2005-2009 Cavium Networks | 6 | * Copyright (C) 2005-2009, 2010 Cavium Networks |
7 | */ | 7 | */ |
8 | #include <linux/kernel.h> | 8 | #include <linux/kernel.h> |
9 | #include <linux/init.h> | 9 | #include <linux/init.h> |
@@ -22,7 +22,7 @@ | |||
22 | * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is | 22 | * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is |
23 | * in use. | 23 | * in use. |
24 | */ | 24 | */ |
25 | static uint64_t msi_free_irq_bitmask; | 25 | static u64 msi_free_irq_bitmask[4]; |
26 | 26 | ||
27 | /* | 27 | /* |
28 | * Each bit in msi_multiple_irq_bitmask tells that the device using | 28 | * Each bit in msi_multiple_irq_bitmask tells that the device using |
@@ -30,7 +30,7 @@ static uint64_t msi_free_irq_bitmask; | |||
30 | * is used so we can disable all of the MSI interrupts when a device | 30 | * is used so we can disable all of the MSI interrupts when a device |
31 | * uses multiple. | 31 | * uses multiple. |
32 | */ | 32 | */ |
33 | static uint64_t msi_multiple_irq_bitmask; | 33 | static u64 msi_multiple_irq_bitmask[4]; |
34 | 34 | ||
35 | /* | 35 | /* |
36 | * This lock controls updates to msi_free_irq_bitmask and | 36 | * This lock controls updates to msi_free_irq_bitmask and |
@@ -38,6 +38,11 @@ static uint64_t msi_multiple_irq_bitmask; | |||
38 | */ | 38 | */ |
39 | static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); | 39 | static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); |
40 | 40 | ||
41 | /* | ||
42 | * Number of MSI IRQs used. This variable is set up in | ||
43 | * the module init time. | ||
44 | */ | ||
45 | static int msi_irq_size; | ||
41 | 46 | ||
42 | /** | 47 | /** |
43 | * Called when a driver request MSI interrupts instead of the | 48 | * Called when a driver request MSI interrupts instead of the |
@@ -54,12 +59,13 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); | |||
54 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) | 59 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
55 | { | 60 | { |
56 | struct msi_msg msg; | 61 | struct msi_msg msg; |
57 | uint16_t control; | 62 | u16 control; |
58 | int configured_private_bits; | 63 | int configured_private_bits; |
59 | int request_private_bits; | 64 | int request_private_bits; |
60 | int irq; | 65 | int irq = 0; |
61 | int irq_step; | 66 | int irq_step; |
62 | uint64_t search_mask; | 67 | u64 search_mask; |
68 | int index; | ||
63 | 69 | ||
64 | /* | 70 | /* |
65 | * Read the MSI config to figure out how many IRQs this device | 71 | * Read the MSI config to figure out how many IRQs this device |
@@ -111,29 +117,31 @@ try_only_one: | |||
111 | * use. | 117 | * use. |
112 | */ | 118 | */ |
113 | spin_lock(&msi_free_irq_bitmask_lock); | 119 | spin_lock(&msi_free_irq_bitmask_lock); |
114 | for (irq = 0; irq < 64; irq += irq_step) { | 120 | for (index = 0; index < msi_irq_size/64; index++) { |
115 | if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) { | 121 | for (irq = 0; irq < 64; irq += irq_step) { |
116 | msi_free_irq_bitmask |= search_mask << irq; | 122 | if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) { |
117 | msi_multiple_irq_bitmask |= (search_mask >> 1) << irq; | 123 | msi_free_irq_bitmask[index] |= search_mask << irq; |
118 | break; | 124 | msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq; |
125 | goto msi_irq_allocated; | ||
126 | } | ||
119 | } | 127 | } |
120 | } | 128 | } |
129 | msi_irq_allocated: | ||
121 | spin_unlock(&msi_free_irq_bitmask_lock); | 130 | spin_unlock(&msi_free_irq_bitmask_lock); |
122 | 131 | ||
123 | /* Make sure the search for available interrupts didn't fail */ | 132 | /* Make sure the search for available interrupts didn't fail */ |
124 | if (irq >= 64) { | 133 | if (irq >= 64) { |
125 | if (request_private_bits) { | 134 | if (request_private_bits) { |
126 | pr_err("arch_setup_msi_irq: Unable to find %d free " | 135 | pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one", |
127 | "interrupts, trying just one", | ||
128 | 1 << request_private_bits); | 136 | 1 << request_private_bits); |
129 | request_private_bits = 0; | 137 | request_private_bits = 0; |
130 | goto try_only_one; | 138 | goto try_only_one; |
131 | } else | 139 | } else |
132 | panic("arch_setup_msi_irq: Unable to find a free MSI " | 140 | panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); |
133 | "interrupt"); | ||
134 | } | 141 | } |
135 | 142 | ||
136 | /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ | 143 | /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ |
144 | irq += index*64; | ||
137 | irq += OCTEON_IRQ_MSI_BIT0; | 145 | irq += OCTEON_IRQ_MSI_BIT0; |
138 | 146 | ||
139 | switch (octeon_dma_bar_type) { | 147 | switch (octeon_dma_bar_type) { |
@@ -169,6 +177,34 @@ try_only_one: | |||
169 | return 0; | 177 | return 0; |
170 | } | 178 | } |
171 | 179 | ||
180 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | ||
181 | { | ||
182 | struct msi_desc *entry; | ||
183 | int ret; | ||
184 | |||
185 | /* | ||
186 | * MSI-X is not supported. | ||
187 | */ | ||
188 | if (type == PCI_CAP_ID_MSIX) | ||
189 | return -EINVAL; | ||
190 | |||
191 | /* | ||
192 | * If an architecture wants to support multiple MSI, it needs to | ||
193 | * override arch_setup_msi_irqs() | ||
194 | */ | ||
195 | if (type == PCI_CAP_ID_MSI && nvec > 1) | ||
196 | return 1; | ||
197 | |||
198 | list_for_each_entry(entry, &dev->msi_list, list) { | ||
199 | ret = arch_setup_msi_irq(dev, entry); | ||
200 | if (ret < 0) | ||
201 | return ret; | ||
202 | if (ret > 0) | ||
203 | return -ENOSPC; | ||
204 | } | ||
205 | |||
206 | return 0; | ||
207 | } | ||
172 | 208 | ||
173 | /** | 209 | /** |
174 | * Called when a device no longer needs its MSI interrupts. All | 210 | * Called when a device no longer needs its MSI interrupts. All |
@@ -179,12 +215,18 @@ try_only_one: | |||
179 | void arch_teardown_msi_irq(unsigned int irq) | 215 | void arch_teardown_msi_irq(unsigned int irq) |
180 | { | 216 | { |
181 | int number_irqs; | 217 | int number_irqs; |
182 | uint64_t bitmask; | 218 | u64 bitmask; |
219 | int index = 0; | ||
220 | int irq0; | ||
183 | 221 | ||
184 | if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63)) | 222 | if ((irq < OCTEON_IRQ_MSI_BIT0) |
223 | || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0)) | ||
185 | panic("arch_teardown_msi_irq: Attempted to teardown illegal " | 224 | panic("arch_teardown_msi_irq: Attempted to teardown illegal " |
186 | "MSI interrupt (%d)", irq); | 225 | "MSI interrupt (%d)", irq); |
226 | |||
187 | irq -= OCTEON_IRQ_MSI_BIT0; | 227 | irq -= OCTEON_IRQ_MSI_BIT0; |
228 | index = irq / 64; | ||
229 | irq0 = irq % 64; | ||
188 | 230 | ||
189 | /* | 231 | /* |
190 | * Count the number of IRQs we need to free by looking at the | 232 | * Count the number of IRQs we need to free by looking at the |
@@ -192,97 +234,198 @@ void arch_teardown_msi_irq(unsigned int irq) | |||
192 | * IRQ is also owned by this device. | 234 | * IRQ is also owned by this device. |
193 | */ | 235 | */ |
194 | number_irqs = 0; | 236 | number_irqs = 0; |
195 | while ((irq+number_irqs < 64) && | 237 | while ((irq0 + number_irqs < 64) && |
196 | (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs)))) | 238 | (msi_multiple_irq_bitmask[index] |
239 | & (1ull << (irq0 + number_irqs)))) | ||
197 | number_irqs++; | 240 | number_irqs++; |
198 | number_irqs++; | 241 | number_irqs++; |
199 | /* Mask with one bit for each IRQ */ | 242 | /* Mask with one bit for each IRQ */ |
200 | bitmask = (1 << number_irqs) - 1; | 243 | bitmask = (1 << number_irqs) - 1; |
201 | /* Shift the mask to the correct bit location */ | 244 | /* Shift the mask to the correct bit location */ |
202 | bitmask <<= irq; | 245 | bitmask <<= irq0; |
203 | if ((msi_free_irq_bitmask & bitmask) != bitmask) | 246 | if ((msi_free_irq_bitmask[index] & bitmask) != bitmask) |
204 | panic("arch_teardown_msi_irq: Attempted to teardown MSI " | 247 | panic("arch_teardown_msi_irq: Attempted to teardown MSI " |
205 | "interrupt (%d) not in use", irq); | 248 | "interrupt (%d) not in use", irq); |
206 | 249 | ||
207 | /* Checks are done, update the in use bitmask */ | 250 | /* Checks are done, update the in use bitmask */ |
208 | spin_lock(&msi_free_irq_bitmask_lock); | 251 | spin_lock(&msi_free_irq_bitmask_lock); |
209 | msi_free_irq_bitmask &= ~bitmask; | 252 | msi_free_irq_bitmask[index] &= ~bitmask; |
210 | msi_multiple_irq_bitmask &= ~bitmask; | 253 | msi_multiple_irq_bitmask[index] &= ~bitmask; |
211 | spin_unlock(&msi_free_irq_bitmask_lock); | 254 | spin_unlock(&msi_free_irq_bitmask_lock); |
212 | } | 255 | } |
213 | 256 | ||
257 | static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); | ||
258 | |||
259 | static u64 msi_rcv_reg[4]; | ||
260 | static u64 mis_ena_reg[4]; | ||
261 | |||
262 | static void octeon_irq_msi_enable_pcie(unsigned int irq) | ||
263 | { | ||
264 | u64 en; | ||
265 | unsigned long flags; | ||
266 | int msi_number = irq - OCTEON_IRQ_MSI_BIT0; | ||
267 | int irq_index = msi_number >> 6; | ||
268 | int irq_bit = msi_number & 0x3f; | ||
269 | |||
270 | raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); | ||
271 | en = cvmx_read_csr(mis_ena_reg[irq_index]); | ||
272 | en |= 1ull << irq_bit; | ||
273 | cvmx_write_csr(mis_ena_reg[irq_index], en); | ||
274 | cvmx_read_csr(mis_ena_reg[irq_index]); | ||
275 | raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); | ||
276 | } | ||
277 | |||
278 | static void octeon_irq_msi_disable_pcie(unsigned int irq) | ||
279 | { | ||
280 | u64 en; | ||
281 | unsigned long flags; | ||
282 | int msi_number = irq - OCTEON_IRQ_MSI_BIT0; | ||
283 | int irq_index = msi_number >> 6; | ||
284 | int irq_bit = msi_number & 0x3f; | ||
285 | |||
286 | raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); | ||
287 | en = cvmx_read_csr(mis_ena_reg[irq_index]); | ||
288 | en &= ~(1ull << irq_bit); | ||
289 | cvmx_write_csr(mis_ena_reg[irq_index], en); | ||
290 | cvmx_read_csr(mis_ena_reg[irq_index]); | ||
291 | raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); | ||
292 | } | ||
293 | |||
294 | static struct irq_chip octeon_irq_chip_msi_pcie = { | ||
295 | .name = "MSI", | ||
296 | .enable = octeon_irq_msi_enable_pcie, | ||
297 | .disable = octeon_irq_msi_disable_pcie, | ||
298 | }; | ||
299 | |||
300 | static void octeon_irq_msi_enable_pci(unsigned int irq) | ||
301 | { | ||
302 | /* | ||
303 | * Octeon PCI doesn't have the ability to mask/unmask MSI | ||
304 | * interrupts individually. Instead of masking/unmasking them | ||
305 | * in groups of 16, we simple assume MSI devices are well | ||
306 | * behaved. MSI interrupts are always enable and the ACK is | ||
307 | * assumed to be enough | ||
308 | */ | ||
309 | } | ||
310 | |||
311 | static void octeon_irq_msi_disable_pci(unsigned int irq) | ||
312 | { | ||
313 | /* See comment in enable */ | ||
314 | } | ||
315 | |||
316 | static struct irq_chip octeon_irq_chip_msi_pci = { | ||
317 | .name = "MSI", | ||
318 | .enable = octeon_irq_msi_enable_pci, | ||
319 | .disable = octeon_irq_msi_disable_pci, | ||
320 | }; | ||
214 | 321 | ||
215 | /* | 322 | /* |
216 | * Called by the interrupt handling code when an MSI interrupt | 323 | * Called by the interrupt handling code when an MSI interrupt |
217 | * occurs. | 324 | * occurs. |
218 | */ | 325 | */ |
219 | static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) | 326 | static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits) |
220 | { | 327 | { |
221 | uint64_t msi_bits; | ||
222 | int irq; | 328 | int irq; |
329 | int bit; | ||
223 | 330 | ||
224 | if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) | 331 | bit = fls64(msi_bits); |
225 | msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0); | 332 | if (bit) { |
226 | else | 333 | bit--; |
227 | msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV); | 334 | /* Acknowledge it first. */ |
228 | irq = fls64(msi_bits); | 335 | cvmx_write_csr(msi_rcv_reg[index], 1ull << bit); |
229 | if (irq) { | 336 | |
230 | irq += OCTEON_IRQ_MSI_BIT0 - 1; | 337 | irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index; |
231 | if (irq_desc[irq].action) { | 338 | do_IRQ(irq); |
232 | do_IRQ(irq); | 339 | return IRQ_HANDLED; |
233 | return IRQ_HANDLED; | ||
234 | } else { | ||
235 | pr_err("Spurious MSI interrupt %d\n", irq); | ||
236 | if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { | ||
237 | /* These chips have PCIe */ | ||
238 | cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, | ||
239 | 1ull << (irq - | ||
240 | OCTEON_IRQ_MSI_BIT0)); | ||
241 | } else { | ||
242 | /* These chips have PCI */ | ||
243 | cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, | ||
244 | 1ull << (irq - | ||
245 | OCTEON_IRQ_MSI_BIT0)); | ||
246 | } | ||
247 | } | ||
248 | } | 340 | } |
249 | return IRQ_NONE; | 341 | return IRQ_NONE; |
250 | } | 342 | } |
251 | 343 | ||
344 | #define OCTEON_MSI_INT_HANDLER_X(x) \ | ||
345 | static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \ | ||
346 | { \ | ||
347 | u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \ | ||
348 | return __octeon_msi_do_interrupt((x), msi_bits); \ | ||
349 | } | ||
350 | |||
351 | /* | ||
352 | * Create octeon_msi_interrupt{0-3} function body | ||
353 | */ | ||
354 | OCTEON_MSI_INT_HANDLER_X(0); | ||
355 | OCTEON_MSI_INT_HANDLER_X(1); | ||
356 | OCTEON_MSI_INT_HANDLER_X(2); | ||
357 | OCTEON_MSI_INT_HANDLER_X(3); | ||
252 | 358 | ||
253 | /* | 359 | /* |
254 | * Initializes the MSI interrupt handling code | 360 | * Initializes the MSI interrupt handling code |
255 | */ | 361 | */ |
256 | int octeon_msi_initialize(void) | 362 | int __init octeon_msi_initialize(void) |
257 | { | 363 | { |
364 | int irq; | ||
365 | struct irq_chip *msi; | ||
366 | |||
367 | if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) { | ||
368 | msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0; | ||
369 | msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1; | ||
370 | msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2; | ||
371 | msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3; | ||
372 | mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0; | ||
373 | mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1; | ||
374 | mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2; | ||
375 | mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3; | ||
376 | msi = &octeon_irq_chip_msi_pcie; | ||
377 | } else { | ||
378 | msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV; | ||
379 | #define INVALID_GENERATE_ADE 0x8700000000000000ULL; | ||
380 | msi_rcv_reg[1] = INVALID_GENERATE_ADE; | ||
381 | msi_rcv_reg[2] = INVALID_GENERATE_ADE; | ||
382 | msi_rcv_reg[3] = INVALID_GENERATE_ADE; | ||
383 | mis_ena_reg[0] = INVALID_GENERATE_ADE; | ||
384 | mis_ena_reg[1] = INVALID_GENERATE_ADE; | ||
385 | mis_ena_reg[2] = INVALID_GENERATE_ADE; | ||
386 | mis_ena_reg[3] = INVALID_GENERATE_ADE; | ||
387 | msi = &octeon_irq_chip_msi_pci; | ||
388 | } | ||
389 | |||
390 | for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) | ||
391 | set_irq_chip_and_handler(irq, msi, handle_simple_irq); | ||
392 | |||
258 | if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { | 393 | if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { |
259 | if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, | 394 | if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, |
260 | IRQF_SHARED, | 395 | 0, "MSI[0:63]", octeon_msi_interrupt0)) |
261 | "MSI[0:63]", octeon_msi_interrupt)) | ||
262 | panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); | 396 | panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); |
397 | |||
398 | if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1, | ||
399 | 0, "MSI[64:127]", octeon_msi_interrupt1)) | ||
400 | panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); | ||
401 | |||
402 | if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2, | ||
403 | 0, "MSI[127:191]", octeon_msi_interrupt2)) | ||
404 | panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); | ||
405 | |||
406 | if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3, | ||
407 | 0, "MSI[192:255]", octeon_msi_interrupt3)) | ||
408 | panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); | ||
409 | |||
410 | msi_irq_size = 256; | ||
263 | } else if (octeon_is_pci_host()) { | 411 | } else if (octeon_is_pci_host()) { |
264 | if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, | 412 | if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, |
265 | IRQF_SHARED, | 413 | 0, "MSI[0:15]", octeon_msi_interrupt0)) |
266 | "MSI[0:15]", octeon_msi_interrupt)) | ||
267 | panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); | 414 | panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); |
268 | 415 | ||
269 | if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt, | 416 | if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0, |
270 | IRQF_SHARED, | 417 | 0, "MSI[16:31]", octeon_msi_interrupt0)) |
271 | "MSI[16:31]", octeon_msi_interrupt)) | ||
272 | panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); | 418 | panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); |
273 | 419 | ||
274 | if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt, | 420 | if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0, |
275 | IRQF_SHARED, | 421 | 0, "MSI[32:47]", octeon_msi_interrupt0)) |
276 | "MSI[32:47]", octeon_msi_interrupt)) | ||
277 | panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); | 422 | panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); |
278 | 423 | ||
279 | if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt, | 424 | if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0, |
280 | IRQF_SHARED, | 425 | 0, "MSI[48:63]", octeon_msi_interrupt0)) |
281 | "MSI[48:63]", octeon_msi_interrupt)) | ||
282 | panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); | 426 | panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); |
283 | 427 | msi_irq_size = 64; | |
284 | } | 428 | } |
285 | return 0; | 429 | return 0; |
286 | } | 430 | } |
287 | |||
288 | subsys_initcall(octeon_msi_initialize); | 431 | subsys_initcall(octeon_msi_initialize); |