aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/nxp
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/nxp')
-rw-r--r--arch/mips/nxp/pnx8550/common/Makefile29
-rw-r--r--arch/mips/nxp/pnx8550/common/gdb_hook.c109
-rw-r--r--arch/mips/nxp/pnx8550/common/int.c238
-rw-r--r--arch/mips/nxp/pnx8550/common/pci.c133
-rw-r--r--arch/mips/nxp/pnx8550/common/platform.c132
-rw-r--r--arch/mips/nxp/pnx8550/common/proc.c112
-rw-r--r--arch/mips/nxp/pnx8550/common/prom.c129
-rw-r--r--arch/mips/nxp/pnx8550/common/reset.c49
-rw-r--r--arch/mips/nxp/pnx8550/common/setup.c157
-rw-r--r--arch/mips/nxp/pnx8550/common/time.c150
-rw-r--r--arch/mips/nxp/pnx8550/jbs/Makefile4
-rw-r--r--arch/mips/nxp/pnx8550/jbs/board_setup.c65
-rw-r--r--arch/mips/nxp/pnx8550/jbs/init.c53
-rw-r--r--arch/mips/nxp/pnx8550/jbs/irqmap.c35
-rw-r--r--arch/mips/nxp/pnx8550/stb810/Makefile4
-rw-r--r--arch/mips/nxp/pnx8550/stb810/board_setup.c49
-rw-r--r--arch/mips/nxp/pnx8550/stb810/irqmap.c22
-rw-r--r--arch/mips/nxp/pnx8550/stb810/prom_init.c46
18 files changed, 1516 insertions, 0 deletions
diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/nxp/pnx8550/common/Makefile
new file mode 100644
index 000000000000..31cc1a5cec3b
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/Makefile
@@ -0,0 +1,29 @@
1#
2# Per Hallsmark, per.hallsmark@mvista.com
3#
4# ########################################################################
5#
6# This program is free software; you can distribute it and/or modify it
7# under the terms of the GNU General Public License (Version 2) as
8# published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13# for more details.
14#
15# You should have received a copy of the GNU General Public License along
16# with this program; if not, write to the Free Software Foundation, Inc.,
17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18#
19# #######################################################################
20#
21# Makefile for the PNX8550 specific kernel interface routines
22# under Linux.
23#
24
25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
26obj-$(CONFIG_PCI) += pci.o
27obj-$(CONFIG_KGDB) += gdb_hook.o
28
29EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/common/gdb_hook.c b/arch/mips/nxp/pnx8550/common/gdb_hook.c
new file mode 100644
index 000000000000..ad4624f6d9bc
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/gdb_hook.c
@@ -0,0 +1,109 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * This is the interface to the remote debugger stub.
23 *
24 */
25#include <linux/types.h>
26#include <linux/serial.h>
27#include <linux/serialP.h>
28#include <linux/serial_reg.h>
29#include <linux/serial_ip3106.h>
30
31#include <asm/serial.h>
32#include <asm/io.h>
33
34#include <uart.h>
35
36static struct serial_state rs_table[IP3106_NR_PORTS] = {
37};
38static struct async_struct kdb_port_info = {0};
39
40void rs_kgdb_hook(int tty_no)
41{
42 struct serial_state *ser = &rs_table[tty_no];
43
44 kdb_port_info.state = ser;
45 kdb_port_info.magic = SERIAL_MAGIC;
46 kdb_port_info.port = tty_no;
47 kdb_port_info.flags = ser->flags;
48
49 /*
50 * Clear all interrupts
51 */
52 /* Clear all the transmitter FIFO counters (pointer and status) */
53 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST;
54 /* Clear all the receiver FIFO counters (pointer and status) */
55 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST;
56 /* Clear all interrupts */
57 ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX |
58 IP3106_UART_INT_ALLTX;
59
60 /*
61 * Now, initialize the UART
62 */
63 ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT;
64 ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud
65}
66
67int putDebugChar(char c)
68{
69 /* Wait until FIFO not full */
70 while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
71 ;
72 /* Send one char */
73 ip3106_fifo(UART_BASE, kdb_port_info.port) = c;
74
75 return 1;
76}
77
78char getDebugChar(void)
79{
80 char ch;
81
82 /* Wait until there is a char in the FIFO */
83 while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) &
84 IP3106_UART_FIFO_RXFIFO) >> 8))
85 ;
86 /* Read one char */
87 ch = ip3106_fifo(UART_BASE, kdb_port_info.port) &
88 IP3106_UART_FIFO_RBRTHR;
89 /* Advance the RX FIFO read pointer */
90 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT;
91 return (ch);
92}
93
94void rs_disable_debug_interrupts(void)
95{
96 ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */
97}
98
99void rs_enable_debug_interrupts(void)
100{
101 /* Clear all the transmitter FIFO counters (pointer and status) */
102 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST;
103 /* Clear all the receiver FIFO counters (pointer and status) */
104 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST;
105 /* Clear all interrupts */
106 ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX |
107 IP3106_UART_INT_ALLTX;
108 ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */
109}
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c
new file mode 100644
index 000000000000..aad03429a5e3
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/int.c
@@ -0,0 +1,238 @@
1/*
2 *
3 * Copyright (C) 2005 Embedded Alley Solutions, Inc
4 * Ported to 2.6.
5 *
6 * Per Hallsmark, per.hallsmark@mvista.com
7 * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
8 * Copyright (C) 2001 Ralf Baechle
9 *
10 * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
11 *
12 * This program is free software; you can distribute it and/or modify it
13 * under the terms of the GNU General Public License (Version 2) as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 *
25 */
26#include <linux/compiler.h>
27#include <linux/init.h>
28#include <linux/irq.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/kernel_stat.h>
33#include <linux/random.h>
34#include <linux/module.h>
35
36#include <asm/io.h>
37#include <asm/gdb-stub.h>
38#include <int.h>
39#include <uart.h>
40
41/* default prio for interrupts */
42/* first one is a no-no so therefore always prio 0 (disabled) */
43static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
44 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9
45 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19
46 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29
47 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39
48 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49
49 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59
50 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69
51 1 // 70
52};
53
54static void hw0_irqdispatch(int irq)
55{
56 /* find out which interrupt */
57 irq = PNX8550_GIC_VECTOR_0 >> 3;
58
59 if (irq == 0) {
60 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
61 return;
62 }
63 do_IRQ(PNX8550_INT_GIC_MIN + irq);
64}
65
66
67static void timer_irqdispatch(int irq)
68{
69 irq = (0x01c0 & read_c0_config7()) >> 6;
70
71 if (unlikely(irq == 0)) {
72 printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
73 return;
74 }
75
76 if (irq & 0x1)
77 do_IRQ(PNX8550_INT_TIMER1);
78 if (irq & 0x2)
79 do_IRQ(PNX8550_INT_TIMER2);
80 if (irq & 0x4)
81 do_IRQ(PNX8550_INT_TIMER3);
82}
83
84asmlinkage void plat_irq_dispatch(void)
85{
86 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
87
88 if (pending & STATUSF_IP2)
89 hw0_irqdispatch(2);
90 else if (pending & STATUSF_IP7) {
91 if (read_c0_config7() & 0x01c0)
92 timer_irqdispatch(7);
93 } else
94 spurious_interrupt();
95}
96
97static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
98{
99 unsigned long status = read_c0_status();
100
101 status &= ~((clr_mask & 0xFF) << 8);
102 status |= (set_mask & 0xFF) << 8;
103
104 write_c0_status(status);
105}
106
107static inline void mask_gic_int(unsigned int irq_nr)
108{
109 /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */
110 PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */
111}
112
113static inline void unmask_gic_int(unsigned int irq_nr)
114{
115 /* set prio mask to lower four bits and enable interrupt */
116 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
117}
118
119static inline void mask_irq(unsigned int irq_nr)
120{
121 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
122 modify_cp0_intmask(1 << irq_nr, 0);
123 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
124 (irq_nr <= PNX8550_INT_GIC_MAX)) {
125 mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
126 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
127 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
128 modify_cp0_intmask(1 << 7, 0);
129 } else {
130 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
131 }
132}
133
134static inline void unmask_irq(unsigned int irq_nr)
135{
136 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
137 modify_cp0_intmask(0, 1 << irq_nr);
138 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
139 (irq_nr <= PNX8550_INT_GIC_MAX)) {
140 unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
141 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
142 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
143 modify_cp0_intmask(0, 1 << 7);
144 } else {
145 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
146 }
147}
148
149int pnx8550_set_gic_priority(int irq, int priority)
150{
151 int gic_irq = irq-PNX8550_INT_GIC_MIN;
152 int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf;
153
154 gic_prio[gic_irq] = priority;
155 PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]);
156
157 return prev_priority;
158}
159
160static struct irq_chip level_irq_type = {
161 .name = "PNX Level IRQ",
162 .ack = mask_irq,
163 .mask = mask_irq,
164 .mask_ack = mask_irq,
165 .unmask = unmask_irq,
166};
167
168static struct irqaction gic_action = {
169 .handler = no_action,
170 .flags = IRQF_DISABLED,
171 .name = "GIC",
172};
173
174static struct irqaction timer_action = {
175 .handler = no_action,
176 .flags = IRQF_DISABLED,
177 .name = "Timer",
178};
179
180void __init arch_init_irq(void)
181{
182 int i;
183 int configPR;
184
185 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
186 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
187 mask_irq(i); /* mask the irq just in case */
188 }
189
190 /* init of GIC/IPC interrupts */
191 /* should be done before cp0 since cp0 init enables the GIC int */
192 for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) {
193 int gic_int_line = i - PNX8550_INT_GIC_MIN;
194 if (gic_int_line == 0 )
195 continue; // don't fiddle with int 0
196 /*
197 * enable change of TARGET, ENABLE and ACTIVE_LOW bits
198 * set TARGET 0 to route through hw0 interrupt
199 * set ACTIVE_LOW 0 active high (correct?)
200 *
201 * We really should setup an interrupt description table
202 * to do this nicely.
203 * Note, PCI INTA is active low on the bus, but inverted
204 * in the GIC, so to us it's active high.
205 */
206 PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
207
208 /* mask/priority is still 0 so we will not get any
209 * interrupts until it is unmasked */
210
211 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
212 }
213
214 /* Priority level 0 */
215 PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0;
216
217 /* Set int vector table address */
218 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
219
220 set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
221 handle_level_irq);
222 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
223
224 /* init of Timer interrupts */
225 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
226 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
227
228 /* Stop Timer 1-3 */
229 configPR = read_c0_config7();
230 configPR |= 0x00000038;
231 write_c0_config7(configPR);
232
233 set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
234 handle_level_irq);
235 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
236}
237
238EXPORT_SYMBOL(pnx8550_set_gic_priority);
diff --git a/arch/mips/nxp/pnx8550/common/pci.c b/arch/mips/nxp/pnx8550/common/pci.c
new file mode 100644
index 000000000000..eee4f3dfc410
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/pci.c
@@ -0,0 +1,133 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * Author: source@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <pci.h>
26#include <glb.h>
27#include <nand.h>
28
29static struct resource pci_io_resource = {
30 .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */
31 .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
32 .name = "pci IO space",
33 .flags = IORESOURCE_IO
34};
35
36static struct resource pci_mem_resource = {
37 .start = PNX8550_PCIMEM,
38 .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
39 .name = "pci memory space",
40 .flags = IORESOURCE_MEM
41};
42
43extern struct pci_ops pnx8550_pci_ops;
44
45static struct pci_controller pnx8550_controller = {
46 .pci_ops = &pnx8550_pci_ops,
47 .io_resource = &pci_io_resource,
48 .mem_resource = &pci_mem_resource,
49};
50
51/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
52static inline unsigned long get_system_mem_size(void)
53{
54 /* Read IP2031_RANK0_ADDR_LO */
55 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
56 /* Read IP2031_RANK1_ADDR_HI */
57 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
58
59 return dram_r1_hi - dram_r0_lo + 1;
60}
61
62static int __init pnx8550_pci_setup(void)
63{
64 int pci_mem_code;
65 int mem_size = get_system_mem_size() >> 20;
66
67 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
68 Bit 1:Enable DAC Powerdown
69 -> 0:DACs are enabled and are working normally
70 1:DACs are powerdown
71 Bit 0:Enable of PCI inta output
72 -> 0 = Disable PCI inta output
73 1 = Enable PCI inta output
74 */
75 PNX8550_GLB2_ENAB_INTA_O = 0;
76
77 /* Calc the PCI mem size code */
78 if (mem_size >= 128)
79 pci_mem_code = SIZE_128M;
80 else if (mem_size >= 64)
81 pci_mem_code = SIZE_64M;
82 else if (mem_size >= 32)
83 pci_mem_code = SIZE_32M;
84 else
85 pci_mem_code = SIZE_16M;
86
87 /* Set PCI_XIO registers */
88 outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
89 outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
90 outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
91 outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
92
93 /* Send memory transaction via PCI_BASE2 */
94 outl(0x00000001, PCI_BASE | PCI_IO);
95
96 /* Unlock the setup register */
97 outl(0xca, PCI_BASE | PCI_UNLOCKREG);
98
99 /*
100 * BAR0 of PNX8550 (pci base 10) must be zero in order for ide
101 * to work, and in order for bus_to_baddr to work without any
102 * hacks.
103 */
104 outl(0x00000000, PCI_BASE | PCI_BASE10);
105
106 /*
107 *These two bars are set by default or the boot code.
108 * However, it's safer to set them here so we're not boot
109 * code dependent.
110 */
111 outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */
112 outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */
113
114 outl(PCI_EN_TA |
115 PCI_EN_PCI2MMI |
116 PCI_EN_XIO |
117 PCI_SETUP_BASE18_SIZE(SIZE_32M) |
118 PCI_SETUP_BASE18_EN |
119 PCI_SETUP_BASE14_EN |
120 PCI_SETUP_BASE10_PREF |
121 PCI_SETUP_BASE10_SIZE(pci_mem_code) |
122 PCI_SETUP_CFGMANAGE_EN |
123 PCI_SETUP_PCIARB_EN,
124 PCI_BASE |
125 PCI_SETUP); /* PCI_SETUP */
126 outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */
127
128 register_pci_controller(&pnx8550_controller);
129
130 return 0;
131}
132
133arch_initcall(pnx8550_pci_setup);
diff --git a/arch/mips/nxp/pnx8550/common/platform.c b/arch/mips/nxp/pnx8550/common/platform.c
new file mode 100644
index 000000000000..c7c763dbe588
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/platform.c
@@ -0,0 +1,132 @@
1/*
2 * Platform device support for NXP PNX8550 SoCs
3 *
4 * Copyright 2005, Embedded Alley Solutions, Inc
5 *
6 * Based on arch/mips/au1000/common/platform.c
7 * Platform device support for Au1x00 SoCs.
8 *
9 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15#include <linux/device.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/resource.h>
19#include <linux/serial.h>
20#include <linux/serial_pnx8xxx.h>
21#include <linux/platform_device.h>
22
23#include <int.h>
24#include <usb.h>
25#include <uart.h>
26
27static struct resource pnx8550_usb_ohci_resources[] = {
28 [0] = {
29 .start = PNX8550_USB_OHCI_OP_BASE,
30 .end = PNX8550_USB_OHCI_OP_BASE +
31 PNX8550_USB_OHCI_OP_LEN,
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .start = PNX8550_INT_USB,
36 .end = PNX8550_INT_USB,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static struct resource pnx8550_uart_resources[] = {
42 [0] = {
43 .start = PNX8550_UART_PORT0,
44 .end = PNX8550_UART_PORT0 + 0xfff,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = PNX8550_UART_INT(0),
49 .end = PNX8550_UART_INT(0),
50 .flags = IORESOURCE_IRQ,
51 },
52 [2] = {
53 .start = PNX8550_UART_PORT1,
54 .end = PNX8550_UART_PORT1 + 0xfff,
55 .flags = IORESOURCE_MEM,
56 },
57 [3] = {
58 .start = PNX8550_UART_INT(1),
59 .end = PNX8550_UART_INT(1),
60 .flags = IORESOURCE_IRQ,
61 },
62};
63
64struct pnx8xxx_port pnx8xxx_ports[] = {
65 [0] = {
66 .port = {
67 .type = PORT_PNX8XXX,
68 .iotype = UPIO_MEM,
69 .membase = (void __iomem *)PNX8550_UART_PORT0,
70 .mapbase = PNX8550_UART_PORT0,
71 .irq = PNX8550_UART_INT(0),
72 .uartclk = 3692300,
73 .fifosize = 16,
74 .flags = UPF_BOOT_AUTOCONF,
75 .line = 0,
76 },
77 },
78 [1] = {
79 .port = {
80 .type = PORT_PNX8XXX,
81 .iotype = UPIO_MEM,
82 .membase = (void __iomem *)PNX8550_UART_PORT1,
83 .mapbase = PNX8550_UART_PORT1,
84 .irq = PNX8550_UART_INT(1),
85 .uartclk = 3692300,
86 .fifosize = 16,
87 .flags = UPF_BOOT_AUTOCONF,
88 .line = 1,
89 },
90 },
91};
92
93/* The dmamask must be set for OHCI to work */
94static u64 ohci_dmamask = ~(u32)0;
95
96static u64 uart_dmamask = ~(u32)0;
97
98static struct platform_device pnx8550_usb_ohci_device = {
99 .name = "pnx8550-ohci",
100 .id = -1,
101 .dev = {
102 .dma_mask = &ohci_dmamask,
103 .coherent_dma_mask = 0xffffffff,
104 },
105 .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources),
106 .resource = pnx8550_usb_ohci_resources,
107};
108
109static struct platform_device pnx8550_uart_device = {
110 .name = "pnx8xxx-uart",
111 .id = -1,
112 .dev = {
113 .dma_mask = &uart_dmamask,
114 .coherent_dma_mask = 0xffffffff,
115 .platform_data = pnx8xxx_ports,
116 },
117 .num_resources = ARRAY_SIZE(pnx8550_uart_resources),
118 .resource = pnx8550_uart_resources,
119};
120
121static struct platform_device *pnx8550_platform_devices[] __initdata = {
122 &pnx8550_usb_ohci_device,
123 &pnx8550_uart_device,
124};
125
126static int __init pnx8550_platform_init(void)
127{
128 return platform_add_devices(pnx8550_platform_devices,
129 ARRAY_SIZE(pnx8550_platform_devices));
130}
131
132arch_initcall(pnx8550_platform_init);
diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/nxp/pnx8550/common/proc.c
new file mode 100644
index 000000000000..18b125e3b65d
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/proc.c
@@ -0,0 +1,112 @@
1/*
2 * This program is free software; you can distribute it and/or modify it
3 * under the terms of the GNU General Public License (Version 2) as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
9 * for more details.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
14 */
15#include <linux/init.h>
16#include <linux/proc_fs.h>
17#include <linux/irq.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/interrupt.h>
21#include <linux/kernel_stat.h>
22#include <linux/random.h>
23
24#include <asm/io.h>
25#include <asm/gdb-stub.h>
26#include <int.h>
27#include <uart.h>
28
29
30static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
31{
32 int len = 0;
33 int configPR = read_c0_config7();
34
35 if (offset==0) {
36 len += sprintf(&page[len], "Timer: count, compare, tc, status\n");
37 len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n",
38 read_c0_count(), read_c0_compare(),
39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on");
40 len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n",
41 read_c0_count2(), read_c0_compare2(),
42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on");
43 len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n",
44 read_c0_count3(), read_c0_compare3(),
45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on");
46 }
47
48 return len;
49}
50
51static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
52{
53 int len = 0;
54
55 if (offset==0) {
56 len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1());
57 len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2());
58 len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3());
59 len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7());
60 len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status());
61 len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause());
62 len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count());
63 len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2());
64 len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3());
65 len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare());
66 len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2());
67 len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3());
68 }
69
70 return len;
71}
72
73static struct proc_dir_entry* pnx8550_dir = NULL;
74static struct proc_dir_entry* pnx8550_timers = NULL;
75static struct proc_dir_entry* pnx8550_registers = NULL;
76
77static int pnx8550_proc_init( void )
78{
79
80 // Create /proc/pnx8550
81 pnx8550_dir = proc_mkdir("pnx8550", NULL);
82 if (!pnx8550_dir) {
83 printk(KERN_ERR "Can't create pnx8550 proc dir\n");
84 return -1;
85 }
86
87 // Create /proc/pnx8550/timers
88 pnx8550_timers = create_proc_read_entry(
89 "timers",
90 0,
91 pnx8550_dir,
92 pnx8550_timers_read,
93 NULL);
94
95 if (!pnx8550_timers)
96 printk(KERN_ERR "Can't create pnx8550 timers proc file\n");
97
98 // Create /proc/pnx8550/registers
99 pnx8550_registers = create_proc_read_entry(
100 "registers",
101 0,
102 pnx8550_dir,
103 pnx8550_registers_read,
104 NULL);
105
106 if (!pnx8550_registers)
107 printk(KERN_ERR "Can't create pnx8550 registers proc file\n");
108
109 return 0;
110}
111
112__initcall(pnx8550_proc_init);
diff --git a/arch/mips/nxp/pnx8550/common/prom.c b/arch/mips/nxp/pnx8550/common/prom.c
new file mode 100644
index 000000000000..2f567452e7ac
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/prom.c
@@ -0,0 +1,129 @@
1/*
2 *
3 * Per Hallsmark, per.hallsmark@mvista.com
4 *
5 * Based on jmr3927/common/prom.c
6 *
7 * 2004 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/string.h>
16#include <linux/serial_pnx8xxx.h>
17
18#include <asm/bootinfo.h>
19#include <uart.h>
20
21/* #define DEBUG_CMDLINE */
22
23extern int prom_argc;
24extern char **prom_argv, **prom_envp;
25
26typedef struct
27{
28 char *name;
29/* char *val; */
30}t_env_var;
31
32
33char * prom_getcmdline(void)
34{
35 return &(arcs_cmdline[0]);
36}
37
38void __init prom_init_cmdline(void)
39{
40 int i;
41
42 arcs_cmdline[0] = '\0';
43 for (i = 0; i < prom_argc; i++) {
44 strcat(arcs_cmdline, prom_argv[i]);
45 strcat(arcs_cmdline, " ");
46 }
47}
48
49char *prom_getenv(char *envname)
50{
51 /*
52 * Return a pointer to the given environment variable.
53 * Environment variables are stored in the form of "memsize=64".
54 */
55
56 t_env_var *env = (t_env_var *)prom_envp;
57 int i;
58
59 i = strlen(envname);
60
61 while(env->name) {
62 if(strncmp(envname, env->name, i) == 0) {
63 return(env->name + strlen(envname) + 1);
64 }
65 env++;
66 }
67 return(NULL);
68}
69
70inline unsigned char str2hexnum(unsigned char c)
71{
72 if(c >= '0' && c <= '9')
73 return c - '0';
74 if(c >= 'a' && c <= 'f')
75 return c - 'a' + 10;
76 if(c >= 'A' && c <= 'F')
77 return c - 'A' + 10;
78 return 0; /* foo */
79}
80
81inline void str2eaddr(unsigned char *ea, unsigned char *str)
82{
83 int i;
84
85 for(i = 0; i < 6; i++) {
86 unsigned char num;
87
88 if((*str == '.') || (*str == ':'))
89 str++;
90 num = str2hexnum(*str++) << 4;
91 num |= (str2hexnum(*str++));
92 ea[i] = num;
93 }
94}
95
96int get_ethernet_addr(char *ethernet_addr)
97{
98 char *ethaddr_str;
99
100 ethaddr_str = prom_getenv("ethaddr");
101 if (!ethaddr_str) {
102 printk("ethaddr not set in boot prom\n");
103 return -1;
104 }
105 str2eaddr(ethernet_addr, ethaddr_str);
106 return 0;
107}
108
109void __init prom_free_prom_memory(void)
110{
111}
112
113extern int pnx8550_console_port;
114
115/* used by early printk */
116void prom_putchar(char c)
117{
118 if (pnx8550_console_port != -1) {
119 /* Wait until FIFO not full */
120 while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) >= 16)
121 ;
122 /* Send one char */
123 ip3106_fifo(UART_BASE, pnx8550_console_port) = c;
124 }
125}
126
127EXPORT_SYMBOL(prom_getcmdline);
128EXPORT_SYMBOL(get_ethernet_addr);
129EXPORT_SYMBOL(str2eaddr);
diff --git a/arch/mips/nxp/pnx8550/common/reset.c b/arch/mips/nxp/pnx8550/common/reset.c
new file mode 100644
index 000000000000..7b2cbc5b2c7c
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/reset.c
@@ -0,0 +1,49 @@
1/*.
2 *
3 * ########################################################################
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * ########################################################################
19 *
20 * Reset the PNX8550 board.
21 *
22 */
23#include <linux/slab.h>
24#include <asm/reboot.h>
25#include <glb.h>
26
27void pnx8550_machine_restart(char *command)
28{
29 char head[] = "************* Machine restart *************";
30 char foot[] = "*******************************************";
31
32 printk("\n\n");
33 printk("%s\n", head);
34 if (command != NULL)
35 printk("* %s\n", command);
36 printk("%s\n", foot);
37
38 PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST;
39}
40
41void pnx8550_machine_halt(void)
42{
43 printk("*** Machine halt. (Not implemented) ***\n");
44}
45
46void pnx8550_machine_power_off(void)
47{
48 printk("*** Machine power off. (Not implemented) ***\n");
49}
diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
new file mode 100644
index 000000000000..92d764c97701
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/setup.c
@@ -0,0 +1,157 @@
1/*
2 *
3 * 2.6 port, Embedded Alley Solutions, Inc
4 *
5 * Based on Per Hallsmark, per.hallsmark@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/ioport.h>
23#include <linux/irq.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/serial_pnx8xxx.h>
28#include <linux/pm.h>
29
30#include <asm/cpu.h>
31#include <asm/bootinfo.h>
32#include <asm/irq.h>
33#include <asm/mipsregs.h>
34#include <asm/reboot.h>
35#include <asm/pgtable.h>
36#include <asm/time.h>
37
38#include <glb.h>
39#include <int.h>
40#include <pci.h>
41#include <uart.h>
42#include <nand.h>
43
44extern void __init board_setup(void);
45extern void pnx8550_machine_restart(char *);
46extern void pnx8550_machine_halt(void);
47extern void pnx8550_machine_power_off(void);
48extern struct resource ioport_resource;
49extern struct resource iomem_resource;
50extern void rs_kgdb_hook(int tty_no);
51extern char *prom_getcmdline(void);
52
53struct resource standard_io_resources[] = {
54 {
55 .start = 0x00,
56 .end = 0x1f,
57 .name = "dma1",
58 .flags = IORESOURCE_BUSY
59 }, {
60 .start = 0x40,
61 .end = 0x5f,
62 .name = "timer",
63 .flags = IORESOURCE_BUSY
64 }, {
65 .start = 0x80,
66 .end = 0x8f,
67 .name = "dma page reg",
68 .flags = IORESOURCE_BUSY
69 }, {
70 .start = 0xc0,
71 .end = 0xdf,
72 .name = "dma2",
73 .flags = IORESOURCE_BUSY
74 },
75};
76
77#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources)
78
79extern struct resource pci_io_resource;
80extern struct resource pci_mem_resource;
81
82/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
83unsigned long get_system_mem_size(void)
84{
85 /* Read IP2031_RANK0_ADDR_LO */
86 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
87 /* Read IP2031_RANK1_ADDR_HI */
88 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
89
90 return dram_r1_hi - dram_r0_lo + 1;
91}
92
93int pnx8550_console_port = -1;
94
95void __init plat_mem_setup(void)
96{
97 int i;
98 char* argptr;
99
100 board_setup(); /* board specific setup */
101
102 _machine_restart = pnx8550_machine_restart;
103 _machine_halt = pnx8550_machine_halt;
104 pm_power_off = pnx8550_machine_power_off;
105
106 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
107 Bit 1:Enable DAC Powerdown
108 -> 0:DACs are enabled and are working normally
109 1:DACs are powerdown
110 Bit 0:Enable of PCI inta output
111 -> 0 = Disable PCI inta output
112 1 = Enable PCI inta output
113 */
114 PNX8550_GLB2_ENAB_INTA_O = 0;
115
116 /* IO/MEM resources. */
117 set_io_port_base(KSEG1);
118 ioport_resource.start = 0;
119 ioport_resource.end = ~0;
120 iomem_resource.start = 0;
121 iomem_resource.end = ~0;
122
123 /* Request I/O space for devices on this board */
124 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
125 request_resource(&ioport_resource, standard_io_resources + i);
126
127 /* Place the Mode Control bit for GPIO pin 16 in primary function */
128 /* Pin 16 is used by UART1, UA1_TX */
129 outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
130 (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
131 PNX8550_GPIO_MC1);
132
133 argptr = prom_getcmdline();
134 if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
135 argptr += strlen("console=ttyS");
136 pnx8550_console_port = *argptr == '0' ? 0 : 1;
137
138 /* We must initialize the UART (console) before early printk */
139 /* Set LCR to 8-bit and BAUD to 38400 (no 5) */
140 ip3106_lcr(UART_BASE, pnx8550_console_port) =
141 PNX8XXX_UART_LCR_8BIT;
142 ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
143 }
144
145#ifdef CONFIG_KGDB
146 argptr = prom_getcmdline();
147 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
148 int line;
149 argptr += strlen("kgdb=ttyS");
150 line = *argptr == '0' ? 0 : 1;
151 rs_kgdb_hook(line);
152 pr_info("KGDB: Using ttyS%i for session, "
153 "please connect your debugger\n", line ? 1 : 0);
154 }
155#endif
156 return;
157}
diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c
new file mode 100644
index 000000000000..62f495b57f93
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/time.c
@@ -0,0 +1,150 @@
1/*
2 * Copyright 2001, 2002, 2003 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
5 *
6 * Common time service routines for MIPS machines. See
7 * Documents/MIPS/README.txt.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sched.h>
18#include <linux/param.h>
19#include <linux/time.h>
20#include <linux/timer.h>
21#include <linux/smp.h>
22#include <linux/kernel_stat.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25
26#include <asm/bootinfo.h>
27#include <asm/cpu.h>
28#include <asm/time.h>
29#include <asm/hardirq.h>
30#include <asm/div64.h>
31#include <asm/debug.h>
32
33#include <int.h>
34#include <cm.h>
35
36static unsigned long cpj;
37
38static cycle_t hpt_read(void)
39{
40 return read_c0_count2();
41}
42
43static struct clocksource pnx_clocksource = {
44 .name = "pnx8xxx",
45 .rating = 200,
46 .read = hpt_read,
47 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
48};
49
50static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
51{
52 struct clock_event_device *c = dev_id;
53
54 /* clear MATCH, signal the event */
55 c->event_handler(c);
56
57 return IRQ_HANDLED;
58}
59
60static struct irqaction pnx8xxx_timer_irq = {
61 .handler = pnx8xxx_timer_interrupt,
62 .flags = IRQF_DISABLED | IRQF_PERCPU,
63 .name = "pnx8xxx_timer",
64};
65
66static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
67{
68 /* Timer 2 clear interrupt */
69 write_c0_compare2(-1);
70 return IRQ_HANDLED;
71}
72
73static struct irqaction monotonic_irqaction = {
74 .handler = monotonic_interrupt,
75 .flags = IRQF_DISABLED,
76 .name = "Monotonic timer",
77};
78
79static int pnx8xxx_set_next_event(unsigned long delta,
80 struct clock_event_device *evt)
81{
82 write_c0_compare(delta);
83 return 0;
84}
85
86static struct clock_event_device pnx8xxx_clockevent = {
87 .name = "pnx8xxx_clockevent",
88 .features = CLOCK_EVT_FEAT_ONESHOT,
89 .set_next_event = pnx8xxx_set_next_event,
90};
91
92static inline void timer_ack(void)
93{
94 write_c0_compare(cpj);
95}
96
97__init void plat_time_init(void)
98{
99 unsigned int configPR;
100 unsigned int n;
101 unsigned int m;
102 unsigned int p;
103 unsigned int pow2p;
104
105 clockevents_register_device(&pnx8xxx_clockevent);
106 clocksource_register(&pnx_clocksource);
107
108 /* Timer 1 start */
109 configPR = read_c0_config7();
110 configPR &= ~0x00000008;
111 write_c0_config7(configPR);
112
113 /* Timer 2 start */
114 configPR = read_c0_config7();
115 configPR &= ~0x00000010;
116 write_c0_config7(configPR);
117
118 /* Timer 3 stop */
119 configPR = read_c0_config7();
120 configPR |= 0x00000020;
121 write_c0_config7(configPR);
122
123
124 /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
125 /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */
126
127 n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
128 m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
129 p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
130 pow2p = (1 << p);
131
132 db_assert(m != 0 && pow2p != 0);
133
134 /*
135 * Compute the frequency as in the PNX8550 User Manual 1.0, p.186
136 * (a.k.a. 8-10). Divide by HZ for a timer offset that results in
137 * HZ timer interrupts per second.
138 */
139 mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
140 cpj = (mips_hpt_frequency + HZ / 2) / HZ;
141 write_c0_count(0);
142 timer_ack();
143
144 /* Setup Timer 2 */
145 write_c0_count2(0);
146 write_c0_compare2(0xffffffff);
147
148 setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq);
149 setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
150}
diff --git a/arch/mips/nxp/pnx8550/jbs/Makefile b/arch/mips/nxp/pnx8550/jbs/Makefile
new file mode 100644
index 000000000000..ad6a8ca7d8ce
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/jbs/Makefile
@@ -0,0 +1,4 @@
1
2# Makefile for the NXP JBS Board.
3
4lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/nxp/pnx8550/jbs/board_setup.c
new file mode 100644
index 000000000000..f92826e0096d
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c
@@ -0,0 +1,65 @@
1/*
2 * JBS Specific board startup routines.
3 *
4 * Copyright 2005, Embedded Alley Solutions, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/init.h>
27#include <linux/sched.h>
28#include <linux/ioport.h>
29#include <linux/mm.h>
30#include <linux/console.h>
31#include <linux/mc146818rtc.h>
32#include <linux/delay.h>
33
34#include <asm/cpu.h>
35#include <asm/bootinfo.h>
36#include <asm/irq.h>
37#include <asm/mipsregs.h>
38#include <asm/reboot.h>
39#include <asm/pgtable.h>
40
41#include <glb.h>
42
43/* CP0 hazard avoidance. */
44#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
45 "nop; nop; nop; nop; nop; nop;\n\t" \
46 ".set reorder\n\t")
47
48void __init board_setup(void)
49{
50 unsigned long config0, configpr;
51
52 config0 = read_c0_config();
53
54 /* clear all three cache coherency fields */
55 config0 &= ~(0x7 | (7<<25) | (7<<28));
56 config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
57 (CONF_CM_DEFAULT<<28));
58 write_c0_config(config0);
59 BARRIER;
60
61 configpr = read_c0_config7();
62 configpr |= (1<<19); /* enable tlb */
63 write_c0_config7(configpr);
64 BARRIER;
65}
diff --git a/arch/mips/nxp/pnx8550/jbs/init.c b/arch/mips/nxp/pnx8550/jbs/init.c
new file mode 100644
index 000000000000..d59b4a4e5e8b
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/jbs/init.c
@@ -0,0 +1,53 @@
1/*
2 *
3 * Copyright 2005 Embedded Alley Solutions, Inc
4 * source@embeddedalley.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/mm.h>
29#include <linux/sched.h>
30#include <linux/bootmem.h>
31#include <asm/addrspace.h>
32#include <asm/bootinfo.h>
33#include <linux/string.h>
34#include <linux/kernel.h>
35
36int prom_argc;
37char **prom_argv, **prom_envp;
38extern void __init prom_init_cmdline(void);
39extern char *prom_getenv(char *envname);
40
41const char *get_system_type(void)
42{
43 return "NXP PNX8550/JBS";
44}
45
46void __init prom_init(void)
47{
48 unsigned long memsize;
49
50 //memsize = 0x02800000; /* Trimedia uses memory above */
51 memsize = 0x08000000; /* Trimedia uses memory above */
52 add_memory_region(0, memsize, BOOT_MEM_RAM);
53}
diff --git a/arch/mips/nxp/pnx8550/jbs/irqmap.c b/arch/mips/nxp/pnx8550/jbs/irqmap.c
new file mode 100644
index 000000000000..7fc89842002c
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/jbs/irqmap.c
@@ -0,0 +1,35 @@
1/*
2 * NXP JBS board irqmap.
3 *
4 * Copyright 2005 Embedded Alley Solutions, Inc
5 * source@embeddealley.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <int.h>
30
31char pnx8550_irq_tab[][5] __initdata = {
32 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
33 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
34 [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
35};
diff --git a/arch/mips/nxp/pnx8550/stb810/Makefile b/arch/mips/nxp/pnx8550/stb810/Makefile
new file mode 100644
index 000000000000..ab91d72c5664
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/stb810/Makefile
@@ -0,0 +1,4 @@
1
2# Makefile for the NXP STB810 Board.
3
4lib-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/nxp/pnx8550/stb810/board_setup.c
new file mode 100644
index 000000000000..1282c27cfcb7
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c
@@ -0,0 +1,49 @@
1/*
2 * STB810 specific board startup routines.
3 *
4 * Based on the arch/mips/nxp/pnx8550/jbs/board_setup.c
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2005 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/init.h>
18#include <linux/sched.h>
19#include <linux/ioport.h>
20#include <linux/mm.h>
21#include <linux/console.h>
22#include <linux/mc146818rtc.h>
23#include <linux/delay.h>
24
25#include <asm/cpu.h>
26#include <asm/bootinfo.h>
27#include <asm/irq.h>
28#include <asm/mipsregs.h>
29#include <asm/reboot.h>
30#include <asm/pgtable.h>
31
32#include <glb.h>
33
34void __init board_setup(void)
35{
36 unsigned long config0, configpr;
37
38 config0 = read_c0_config();
39
40 /* clear all three cache coherency fields */
41 config0 &= ~(0x7 | (7<<25) | (7<<28));
42 config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
43 (CONF_CM_DEFAULT<<28));
44 write_c0_config(config0);
45
46 configpr = read_c0_config7();
47 configpr |= (1<<19); /* enable tlb */
48 write_c0_config7(configpr);
49}
diff --git a/arch/mips/nxp/pnx8550/stb810/irqmap.c b/arch/mips/nxp/pnx8550/stb810/irqmap.c
new file mode 100644
index 000000000000..8c034963ddcd
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/stb810/irqmap.c
@@ -0,0 +1,22 @@
1/*
2 * NXP STB810 board irqmap.
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/init.h>
16#include <int.h>
17
18char pnx8550_irq_tab[][5] __initdata = {
19 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
20 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
21 [10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
22};
diff --git a/arch/mips/nxp/pnx8550/stb810/prom_init.c b/arch/mips/nxp/pnx8550/stb810/prom_init.c
new file mode 100644
index 000000000000..ca7f4ada0640
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/stb810/prom_init.c
@@ -0,0 +1,46 @@
1/*
2 * STB810 specific prom routines
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/bootmem.h>
19#include <asm/addrspace.h>
20#include <asm/bootinfo.h>
21#include <linux/string.h>
22#include <linux/kernel.h>
23
24int prom_argc;
25char **prom_argv, **prom_envp;
26extern void __init prom_init_cmdline(void);
27extern char *prom_getenv(char *envname);
28
29const char *get_system_type(void)
30{
31 return "NXP PNX8950/STB810";
32}
33
34void __init prom_init(void)
35{
36 unsigned long memsize;
37
38 prom_argc = (int) fw_arg0;
39 prom_argv = (char **) fw_arg1;
40 prom_envp = (char **) fw_arg2;
41
42 prom_init_cmdline();
43
44 memsize = 0x08000000; /* Trimedia uses memory above */
45 add_memory_region(0, memsize, BOOT_MEM_RAM);
46}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 11:42:45 -0500