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-rw-r--r--arch/mips/netlogic/Kconfig3
-rw-r--r--arch/mips/netlogic/Makefile3
-rw-r--r--arch/mips/netlogic/Platform13
-rw-r--r--arch/mips/netlogic/common/Makefile3
-rw-r--r--arch/mips/netlogic/common/earlycons.c (renamed from arch/mips/netlogic/xlr/xlr_console.c)22
-rw-r--r--arch/mips/netlogic/common/irq.c238
-rw-r--r--arch/mips/netlogic/common/smp.c (renamed from arch/mips/netlogic/xlr/smp.c)152
-rw-r--r--arch/mips/netlogic/common/smpboot.S272
-rw-r--r--arch/mips/netlogic/common/time.c (renamed from arch/mips/netlogic/xlr/time.c)6
-rw-r--r--arch/mips/netlogic/xlp/Makefile2
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c111
-rw-r--r--arch/mips/netlogic/xlp/platform.c108
-rw-r--r--arch/mips/netlogic/xlp/setup.c105
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c102
-rw-r--r--arch/mips/netlogic/xlr/Makefile7
-rw-r--r--arch/mips/netlogic/xlr/irq.c300
-rw-r--r--arch/mips/netlogic/xlr/platform.c31
-rw-r--r--arch/mips/netlogic/xlr/setup.c31
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c (renamed from arch/mips/netlogic/xlr/smpboot.S)80
19 files changed, 1137 insertions, 452 deletions
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index a5ca743613f2..75bec44b5856 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -1,5 +1,2 @@
1config NLM_COMMON 1config NLM_COMMON
2 bool 2 bool
3
4config NLM_XLR
5 bool
diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile
new file mode 100644
index 000000000000..36d169b2ca6d
--- /dev/null
+++ b/arch/mips/netlogic/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_NLM_COMMON) += common/
2obj-$(CONFIG_CPU_XLR) += xlr/
3obj-$(CONFIG_CPU_XLP) += xlp/
diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform
index b648b487fd66..cdfc9abbbb7b 100644
--- a/arch/mips/netlogic/Platform
+++ b/arch/mips/netlogic/Platform
@@ -1,16 +1,17 @@
1# 1#
2# NETLOGIC includes 2# NETLOGIC includes
3# 3#
4cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic 4cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic
5cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic 5cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic
6 6
7# 7#
8# use mips64 if xlr is not available 8# use mips64 if xlr is not available
9# 9#
10cflags-$(CONFIG_NLM_XLR) += $(call cc-option,-march=xlr,-march=mips64) 10cflags-$(CONFIG_CPU_XLR) += $(call cc-option,-march=xlr,-march=mips64)
11cflags-$(CONFIG_CPU_XLP) += $(call cc-option,-march=xlp,-march=mips64r2)
11 12
12# 13#
13# NETLOGIC XLR/XLS SoC, Simulator and boards 14# NETLOGIC processor support
14# 15#
15core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ 16platform-$(CONFIG_NLM_COMMON) += netlogic/
16load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 17load-$(CONFIG_NLM_COMMON) += 0xffffffff80100000
diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile
new file mode 100644
index 000000000000..291372a086f5
--- /dev/null
+++ b/arch/mips/netlogic/common/Makefile
@@ -0,0 +1,3 @@
1obj-y += irq.o time.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o
3obj-$(CONFIG_EARLY_PRINTK) += earlycons.o
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/common/earlycons.c
index 759df0692201..f193f7b3bd81 100644
--- a/arch/mips/netlogic/xlr/xlr_console.c
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -33,14 +33,28 @@
33 */ 33 */
34 34
35#include <linux/types.h> 35#include <linux/types.h>
36#include <linux/serial_reg.h>
37
38#include <asm/mipsregs.h>
39#include <asm/netlogic/haldefs.h>
40
41#if defined(CONFIG_CPU_XLP)
42#include <asm/netlogic/xlp-hal/iomap.h>
43#include <asm/netlogic/xlp-hal/uart.h>
44#elif defined(CONFIG_CPU_XLR)
36#include <asm/netlogic/xlr/iomap.h> 45#include <asm/netlogic/xlr/iomap.h>
46#endif
37 47
38void prom_putchar(char c) 48void prom_putchar(char c)
39{ 49{
40 nlm_reg_t *mmio; 50 uint64_t uartbase;
41 51
42 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 52#if defined(CONFIG_CPU_XLP)
43 while (netlogic_read_reg(mmio, 0x5) == 0) 53 uartbase = nlm_get_uart_regbase(0, 0);
54#elif defined(CONFIG_CPU_XLR)
55 uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
56#endif
57 while (nlm_read_reg(uartbase, UART_LSR) == 0)
44 ; 58 ;
45 netlogic_write_reg(mmio, 0x0, c); 59 nlm_write_reg(uartbase, UART_TX, c);
46} 60}
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
new file mode 100644
index 000000000000..49a4f6cf71e5
--- /dev/null
+++ b/arch/mips/netlogic/common/irq.c
@@ -0,0 +1,238 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41#include <linux/slab.h>
42#include <linux/irq.h>
43
44#include <asm/errno.h>
45#include <asm/signal.h>
46#include <asm/system.h>
47#include <asm/ptrace.h>
48#include <asm/mipsregs.h>
49#include <asm/thread_info.h>
50
51#include <asm/netlogic/mips-extns.h>
52#include <asm/netlogic/interrupt.h>
53#include <asm/netlogic/haldefs.h>
54#include <asm/netlogic/common.h>
55
56#if defined(CONFIG_CPU_XLP)
57#include <asm/netlogic/xlp-hal/iomap.h>
58#include <asm/netlogic/xlp-hal/xlp.h>
59#include <asm/netlogic/xlp-hal/pic.h>
60#elif defined(CONFIG_CPU_XLR)
61#include <asm/netlogic/xlr/iomap.h>
62#include <asm/netlogic/xlr/pic.h>
63#else
64#error "Unknown CPU"
65#endif
66/*
67 * These are the routines that handle all the low level interrupt stuff.
68 * Actions handled here are: initialization of the interrupt map, requesting of
69 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
70 * for interrupt lines
71 */
72
73/* Globals */
74static uint64_t nlm_irq_mask;
75static DEFINE_SPINLOCK(nlm_pic_lock);
76
77static void xlp_pic_enable(struct irq_data *d)
78{
79 unsigned long flags;
80 int irt;
81
82 irt = nlm_irq_to_irt(d->irq);
83 if (irt == -1)
84 return;
85 spin_lock_irqsave(&nlm_pic_lock, flags);
86 nlm_pic_enable_irt(nlm_pic_base, irt);
87 spin_unlock_irqrestore(&nlm_pic_lock, flags);
88}
89
90static void xlp_pic_disable(struct irq_data *d)
91{
92 unsigned long flags;
93 int irt;
94
95 irt = nlm_irq_to_irt(d->irq);
96 if (irt == -1)
97 return;
98 spin_lock_irqsave(&nlm_pic_lock, flags);
99 nlm_pic_disable_irt(nlm_pic_base, irt);
100 spin_unlock_irqrestore(&nlm_pic_lock, flags);
101}
102
103static void xlp_pic_mask_ack(struct irq_data *d)
104{
105 uint64_t mask = 1ull << d->irq;
106
107 write_c0_eirr(mask); /* ack by writing EIRR */
108}
109
110static void xlp_pic_unmask(struct irq_data *d)
111{
112 void *hd = irq_data_get_irq_handler_data(d);
113 int irt;
114
115 irt = nlm_irq_to_irt(d->irq);
116 if (irt == -1)
117 return;
118
119 if (hd) {
120 void (*extra_ack)(void *) = hd;
121 extra_ack(d);
122 }
123 /* Ack is a single write, no need to lock */
124 nlm_pic_ack(nlm_pic_base, irt);
125}
126
127static struct irq_chip xlp_pic = {
128 .name = "XLP-PIC",
129 .irq_enable = xlp_pic_enable,
130 .irq_disable = xlp_pic_disable,
131 .irq_mask_ack = xlp_pic_mask_ack,
132 .irq_unmask = xlp_pic_unmask,
133};
134
135static void cpuintr_disable(struct irq_data *d)
136{
137 uint64_t eimr;
138 uint64_t mask = 1ull << d->irq;
139
140 eimr = read_c0_eimr();
141 write_c0_eimr(eimr & ~mask);
142}
143
144static void cpuintr_enable(struct irq_data *d)
145{
146 uint64_t eimr;
147 uint64_t mask = 1ull << d->irq;
148
149 eimr = read_c0_eimr();
150 write_c0_eimr(eimr | mask);
151}
152
153static void cpuintr_ack(struct irq_data *d)
154{
155 uint64_t mask = 1ull << d->irq;
156
157 write_c0_eirr(mask);
158}
159
160static void cpuintr_nop(struct irq_data *d)
161{
162 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
163}
164
165/*
166 * Chip definition for CPU originated interrupts(timer, msg) and
167 * IPIs
168 */
169struct irq_chip nlm_cpu_intr = {
170 .name = "XLP-CPU-INTR",
171 .irq_enable = cpuintr_enable,
172 .irq_disable = cpuintr_disable,
173 .irq_mask = cpuintr_nop,
174 .irq_ack = cpuintr_nop,
175 .irq_eoi = cpuintr_ack,
176};
177
178void __init init_nlm_common_irqs(void)
179{
180 int i, irq, irt;
181
182 for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
183 irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
184
185 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
186 irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
187
188#ifdef CONFIG_SMP
189 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
190 nlm_smp_function_ipi_handler);
191 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
192 nlm_smp_resched_ipi_handler);
193 nlm_irq_mask |=
194 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
195#endif
196
197 for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
198 irt = nlm_irq_to_irt(irq);
199 if (irt == -1)
200 continue;
201 nlm_irq_mask |= (1ULL << irq);
202 nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
203 }
204
205 nlm_irq_mask |= (1ULL << IRQ_TIMER);
206}
207
208void __init arch_init_irq(void)
209{
210 /* Initialize the irq descriptors */
211 init_nlm_common_irqs();
212
213 write_c0_eimr(nlm_irq_mask);
214}
215
216void __cpuinit nlm_smp_irq_init(void)
217{
218 /* set interrupt mask for non-zero cpus */
219 write_c0_eimr(nlm_irq_mask);
220}
221
222asmlinkage void plat_irq_dispatch(void)
223{
224 uint64_t eirr;
225 int i;
226
227 eirr = read_c0_eirr() & read_c0_eimr();
228 if (eirr & (1 << IRQ_TIMER)) {
229 do_IRQ(IRQ_TIMER);
230 return;
231 }
232
233 i = __ilog2_u64(eirr);
234 if (i == -1)
235 return;
236
237 do_IRQ(i);
238}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/common/smp.c
index 080284ded508..db17f49886c2 100644
--- a/arch/mips/netlogic/xlr/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -42,31 +42,29 @@
42 42
43#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h> 44#include <asm/netlogic/mips-extns.h>
45 45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47
48#if defined(CONFIG_CPU_XLP)
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#elif defined(CONFIG_CPU_XLR)
46#include <asm/netlogic/xlr/iomap.h> 53#include <asm/netlogic/xlr/iomap.h>
47#include <asm/netlogic/xlr/pic.h> 54#include <asm/netlogic/xlr/pic.h>
48#include <asm/netlogic/xlr/xlr.h> 55#include <asm/netlogic/xlr/xlr.h>
56#else
57#error "Unknown CPU"
58#endif
49 59
50void core_send_ipi(int logical_cpu, unsigned int action) 60void nlm_send_ipi_single(int logical_cpu, unsigned int action)
51{ 61{
52 int cpu = cpu_logical_map(logical_cpu); 62 int cpu = cpu_logical_map(logical_cpu);
53 u32 tid = cpu & 0x3;
54 u32 pid = (cpu >> 2) & 0x07;
55 u32 ipi = (tid << 16) | (pid << 20);
56 63
57 if (action & SMP_CALL_FUNCTION) 64 if (action & SMP_CALL_FUNCTION)
58 ipi |= IRQ_IPI_SMP_FUNCTION; 65 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
59 else if (action & SMP_RESCHEDULE_YOURSELF) 66 if (action & SMP_RESCHEDULE_YOURSELF)
60 ipi |= IRQ_IPI_SMP_RESCHEDULE; 67 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
61 else
62 return;
63
64 pic_send_ipi(ipi);
65}
66
67void nlm_send_ipi_single(int cpu, unsigned int action)
68{
69 core_send_ipi(cpu, action);
70} 68}
71 69
72void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) 70void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -74,29 +72,35 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
74 int cpu; 72 int cpu;
75 73
76 for_each_cpu(cpu, mask) { 74 for_each_cpu(cpu, mask) {
77 core_send_ipi(cpu, action); 75 nlm_send_ipi_single(cpu, action);
78 } 76 }
79} 77}
80 78
81/* IRQ_IPI_SMP_FUNCTION Handler */ 79/* IRQ_IPI_SMP_FUNCTION Handler */
82void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) 80void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
83{ 81{
82 write_c0_eirr(1ull << irq);
84 smp_call_function_interrupt(); 83 smp_call_function_interrupt();
85} 84}
86 85
87/* IRQ_IPI_SMP_RESCHEDULE handler */ 86/* IRQ_IPI_SMP_RESCHEDULE handler */
88void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) 87void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
89{ 88{
89 write_c0_eirr(1ull << irq);
90 scheduler_ipi(); 90 scheduler_ipi();
91} 91}
92 92
93/* 93/*
94 * Called before going into mips code, early cpu init 94 * Called before going into mips code, early cpu init
95 */ 95 */
96void nlm_early_init_secondary(void) 96void nlm_early_init_secondary(int cpu)
97{ 97{
98 change_c0_config(CONF_CM_CMASK, 0x3);
98 write_c0_ebase((uint32_t)nlm_common_ebase); 99 write_c0_ebase((uint32_t)nlm_common_ebase);
99 /* TLB partition here later */ 100#ifdef CONFIG_CPU_XLP
101 if (hard_smp_processor_id() % 4 == 0)
102 xlp_mmu_init();
103#endif
100} 104}
101 105
102/* 106/*
@@ -104,9 +108,16 @@ void nlm_early_init_secondary(void)
104 */ 108 */
105static void __cpuinit nlm_init_secondary(void) 109static void __cpuinit nlm_init_secondary(void)
106{ 110{
111 current_cpu_data.core = hard_smp_processor_id() / 4;
107 nlm_smp_irq_init(); 112 nlm_smp_irq_init();
108} 113}
109 114
115void nlm_prepare_cpus(unsigned int max_cpus)
116{
117 /* declare we are SMT capable */
118 smp_num_siblings = nlm_threads_per_core;
119}
120
110void nlm_smp_finish(void) 121void nlm_smp_finish(void)
111{ 122{
112#ifdef notyet 123#ifdef notyet
@@ -123,10 +134,10 @@ void nlm_cpus_done(void)
123 * Boot all other cpus in the system, initialize them, and bring them into 134 * Boot all other cpus in the system, initialize them, and bring them into
124 * the boot function 135 * the boot function
125 */ 136 */
126int nlm_cpu_unblock[NR_CPUS];
127int nlm_cpu_ready[NR_CPUS]; 137int nlm_cpu_ready[NR_CPUS];
128unsigned long nlm_next_gp; 138unsigned long nlm_next_gp;
129unsigned long nlm_next_sp; 139unsigned long nlm_next_sp;
140
130cpumask_t phys_cpu_present_map; 141cpumask_t phys_cpu_present_map;
131 142
132void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) 143void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
@@ -140,7 +151,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
140 151
141 /* barrier */ 152 /* barrier */
142 __sync(); 153 __sync();
143 nlm_cpu_unblock[cpu] = 1; 154 nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1);
144} 155}
145 156
146void __init nlm_smp_setup(void) 157void __init nlm_smp_setup(void)
@@ -159,8 +170,8 @@ void __init nlm_smp_setup(void)
159 num_cpus = 1; 170 num_cpus = 1;
160 for (i = 0; i < NR_CPUS; i++) { 171 for (i = 0; i < NR_CPUS; i++) {
161 /* 172 /*
162 * BSP is not set in nlm_cpu_ready array, it is only for 173 * nlm_cpu_ready array is not set for the boot_cpu,
163 * ASPs (goto see smpboot.S) 174 * it is only set for ASPs (see smpboot.S)
164 */ 175 */
165 if (nlm_cpu_ready[i]) { 176 if (nlm_cpu_ready[i]) {
166 cpu_set(i, phys_cpu_present_map); 177 cpu_set(i, phys_cpu_present_map);
@@ -176,10 +187,75 @@ void __init nlm_smp_setup(void)
176 (unsigned long)cpu_possible_map.bits[0]); 187 (unsigned long)cpu_possible_map.bits[0]);
177 188
178 pr_info("Detected %i Slave CPU(s)\n", num_cpus); 189 pr_info("Detected %i Slave CPU(s)\n", num_cpus);
190 nlm_set_nmi_handler(nlm_boot_secondary_cpus);
179} 191}
180 192
181void nlm_prepare_cpus(unsigned int max_cpus) 193static int nlm_parse_cpumask(u32 cpu_mask)
194{
195 uint32_t core0_thr_mask, core_thr_mask;
196 int threadmode, i;
197
198 core0_thr_mask = cpu_mask & 0xf;
199 switch (core0_thr_mask) {
200 case 1:
201 nlm_threads_per_core = 1;
202 threadmode = 0;
203 break;
204 case 3:
205 nlm_threads_per_core = 2;
206 threadmode = 2;
207 break;
208 case 0xf:
209 nlm_threads_per_core = 4;
210 threadmode = 3;
211 break;
212 default:
213 goto unsupp;
214 }
215
216 /* Verify other cores CPU masks */
217 nlm_coremask = 1;
218 nlm_cpumask = core0_thr_mask;
219 for (i = 1; i < 8; i++) {
220 core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
221 if (core_thr_mask) {
222 if (core_thr_mask != core0_thr_mask)
223 goto unsupp;
224 nlm_coremask |= 1 << i;
225 nlm_cpumask |= core0_thr_mask << (4 * i);
226 }
227 }
228 return threadmode;
229
230unsupp:
231 panic("Unsupported CPU mask %x\n", cpu_mask);
232 return 0;
233}
234
235int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
182{ 236{
237 unsigned long reset_vec;
238 char *reset_data;
239 int threadmode;
240
241 /* Update reset entry point with CPU init code */
242 reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
243 memcpy((void *)reset_vec, (void *)nlm_reset_entry,
244 (nlm_reset_entry_end - nlm_reset_entry));
245
246 /* verify the mask and setup core config variables */
247 threadmode = nlm_parse_cpumask(wakeup_mask);
248
249 /* Setup CPU init parameters */
250 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
251 *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode;
252
253#ifdef CONFIG_CPU_XLP
254 xlp_wakeup_secondary_cpus();
255#else
256 xlr_wakeup_secondary_cpus();
257#endif
258 return 0;
183} 259}
184 260
185struct plat_smp_ops nlm_smp_ops = { 261struct plat_smp_ops nlm_smp_ops = {
@@ -192,29 +268,3 @@ struct plat_smp_ops nlm_smp_ops = {
192 .smp_setup = nlm_smp_setup, 268 .smp_setup = nlm_smp_setup,
193 .prepare_cpus = nlm_prepare_cpus, 269 .prepare_cpus = nlm_prepare_cpus,
194}; 270};
195
196unsigned long secondary_entry_point;
197
198int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
199{
200 unsigned int tid, pid, ipi, i, boot_cpu;
201 void *reset_vec;
202
203 secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
204 reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
205 memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
206 boot_cpu = hard_smp_processor_id();
207
208 for (i = 0; i < NR_CPUS; i++) {
209 if (i == boot_cpu)
210 continue;
211 if (wakeup_mask & (1u << i)) {
212 tid = i & 0x3;
213 pid = (i >> 2) & 0x7;
214 ipi = (tid << 16) | (pid << 20) | (1 << 8);
215 pic_send_ipi(ipi);
216 }
217 }
218
219 return 0;
220}
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
new file mode 100644
index 000000000000..c138b1a6dec3
--- /dev/null
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -0,0 +1,272 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36
37#include <asm/asm.h>
38#include <asm/asm-offsets.h>
39#include <asm/regdef.h>
40#include <asm/mipsregs.h>
41#include <asm/stackframe.h>
42#include <asm/asmmacro.h>
43#include <asm/addrspace.h>
44
45#include <asm/netlogic/common.h>
46
47#include <asm/netlogic/xlp-hal/iomap.h>
48#include <asm/netlogic/xlp-hal/xlp.h>
49#include <asm/netlogic/xlp-hal/sys.h>
50#include <asm/netlogic/xlp-hal/cpucontrol.h>
51
52#define CP0_EBASE $15
53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4
56
57.macro __config_lsu
58 li t0, LSU_DEFEATURE
59 mfcr t1, t0
60
61 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
62 or t1, t1, t2
63 li t2, ~0xe /* S1RCM */
64 and t1, t1, t2
65 mtcr t1, t0
66
67 li t0, SCHED_DEFEATURE
68 lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */
69 mtcr t1, t0
70.endm
71
72/*
73 * The cores can come start when they are woken up. This is also the NMI
74 * entry, so check that first.
75 *
76 * The data corresponding to reset is stored at RESET_DATA_PHYS location,
77 * this will have the thread mask (used when core is woken up) and the
78 * current NMI handler in case we reached here for an NMI.
79 *
80 * When a core or thread is newly woken up, it loops in a 'wait'. When
81 * the CPU really needs waking up, we send an NMI to it, with the NMI
82 * handler set to prom_boot_secondary_cpus
83 */
84
85 .set noreorder
86 .set noat
87 .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
88
89FEXPORT(nlm_reset_entry)
90 dmtc0 k0, $22, 6
91 dmtc0 k1, $22, 7
92 mfc0 k0, CP0_STATUS
93 li k1, 0x80000
94 and k1, k0, k1
95 beqz k1, 1f /* go to real reset entry */
96 nop
97 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
98 ld k0, BOOT_NMI_HANDLER(k1)
99 jr k0
100 nop
101
1021: /* Entry point on core wakeup */
103 mfc0 t0, CP0_EBASE, 1
104 mfc0 t1, CP0_EBASE, 1
105 srl t1, 5
106 andi t1, 0x3 /* t1 <- node */
107 li t2, 0x40000
108 mul t3, t2, t1 /* t3 = node * 0x40000 */
109 srl t0, t0, 2
110 and t0, t0, 0x7 /* t0 <- core */
111 li t1, 0x1
112 sll t0, t1, t0
113 nor t0, t0, zero /* t0 <- ~(1 << core) */
114 li t2, SYS_CPU_COHERENT_BASE(0)
115 add t2, t2, t3 /* t2 <- SYS offset for node */
116 lw t1, 0(t2)
117 and t1, t1, t0
118 sw t1, 0(t2)
119
120 /* read back to ensure complete */
121 lw t1, 0(t2)
122 sync
123
124 /* Configure LSU on Non-0 Cores. */
125 __config_lsu
126
127/*
128 * Wake up sibling threads from the initial thread in
129 * a core.
130 */
131EXPORT(nlm_boot_siblings)
132 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
133 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
134 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
135 mfcr t2, t0
136 or t2, t2, t1
137 mtcr t2, t0
138
139 /*
140 * The new hardware thread starts at the next instruction
141 * For all the cases other than core 0 thread 0, we will
142 * jump to the secondary wait function.
143 */
144 mfc0 v0, CP0_EBASE, 1
145 andi v0, 0x7f /* v0 <- node/core */
146
147#if 1
148 /* A0 errata - Write MMU_SETUP after changing thread mode register. */
149 andi v1, v0, 0x3 /* v1 <- thread id */
150 bnez v1, 2f
151 nop
152
153 li t0, MMU_SETUP
154 li t1, 0
155 mtcr t1, t0
156 ehb
157#endif
158
1592: beqz v0, 4f
160 nop
161
162 /* setup status reg */
163 mfc0 t1, CP0_STATUS
164 li t0, ST0_BEV
165 or t1, t0
166 xor t1, t0
167#ifdef CONFIG_64BIT
168 ori t1, ST0_KX
169#endif
170 mtc0 t1, CP0_STATUS
171 /* mark CPU ready */
172 PTR_LA t1, nlm_cpu_ready
173 sll v1, v0, 2
174 PTR_ADDU t1, v1
175 li t2, 1
176 sw t2, 0(t1)
177 /* Wait until NMI hits */
1783: wait
179 j 3b
180 nop
181
182 /*
183 * For the boot CPU, we have to restore registers and
184 * return
185 */
1864: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
187 li t1, 0xfadebeef
188 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
189 PTR_SUBU sp, t0, PT_SIZE
190 RESTORE_ALL
191 jr ra
192 nop
193EXPORT(nlm_reset_entry_end)
194
195FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
196 __config_lsu
197 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
198 SAVE_ALL
199 sync
200 /* find the location to which nlm_boot_siblings was relocated */
201 li t0, CKSEG1ADDR(RESET_VEC_PHYS)
202 dla t1, nlm_reset_entry
203 dla t2, nlm_boot_siblings
204 dsubu t2, t1
205 daddu t2, t0
206 /* call it */
207 jr t2
208 nop
209 /* not reached */
210
211 __CPUINIT
212NESTED(nlm_boot_secondary_cpus, 16, sp)
213 PTR_LA t1, nlm_next_sp
214 PTR_L sp, 0(t1)
215 PTR_LA t1, nlm_next_gp
216 PTR_L gp, 0(t1)
217
218 /* a0 has the processor id */
219 PTR_LA t0, nlm_early_init_secondary
220 jalr t0
221 nop
222
223 PTR_LA t0, smp_bootstrap
224 jr t0
225 nop
226END(nlm_boot_secondary_cpus)
227 __FINIT
228
229/*
230 * In case of RMIboot bootloader which is used on XLR boards, the CPUs
231 * be already woken up and waiting in bootloader code.
232 * This will get them out of the bootloader code and into linux. Needed
233 * because the bootloader area will be taken and initialized by linux.
234 */
235 __CPUINIT
236NESTED(nlm_rmiboot_preboot, 16, sp)
237 mfc0 t0, $15, 1 # read ebase
238 andi t0, 0x1f # t0 has the processor_id()
239 andi t2, t0, 0x3 # thread no
240 sll t0, 2 # offset in cpu array
241
242 PTR_LA t1, nlm_cpu_ready # mark CPU ready
243 PTR_ADDU t1, t0
244 li t3, 1
245 sw t3, 0(t1)
246
247 bnez t2, 1f # skip thread programming
248 nop # for non zero hw threads
249
250 /*
251 * MMU setup only for first thread in core
252 */
253 li t0, 0x400
254 mfcr t1, t0
255 li t2, 6 # XLR thread mode mask
256 nor t3, t2, zero
257 and t2, t1, t2 # t2 - current thread mode
258 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
259 lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode
260 sll v1, 1
261 beq v1, t2, 1f # same as request value
262 nop # nothing to do */
263
264 and t2, t1, t3 # mask out old thread mode
265 or t1, t2, v1 # put in new value
266 mtcr t1, t0 # update core control
267
2681: wait
269 j 1b
270 nop
271END(nlm_rmiboot_preboot)
272 __FINIT
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/common/time.c
index 0d81b262593c..bd3e498157ff 100644
--- a/arch/mips/netlogic/xlr/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -36,7 +36,7 @@
36 36
37#include <asm/time.h> 37#include <asm/time.h>
38#include <asm/netlogic/interrupt.h> 38#include <asm/netlogic/interrupt.h>
39#include <asm/netlogic/psb-bootinfo.h> 39#include <asm/netlogic/common.h>
40 40
41unsigned int __cpuinit get_c0_compare_int(void) 41unsigned int __cpuinit get_c0_compare_int(void)
42{ 42{
@@ -45,7 +45,7 @@ unsigned int __cpuinit get_c0_compare_int(void)
45 45
46void __init plat_time_init(void) 46void __init plat_time_init(void)
47{ 47{
48 mips_hpt_frequency = nlm_prom_info.cpu_frequency; 48 mips_hpt_frequency = nlm_get_cpu_frequency();
49 pr_info("MIPS counter frequency [%ld]\n", 49 pr_info("MIPS counter frequency [%ld]\n",
50 (unsigned long)mips_hpt_frequency); 50 (unsigned long)mips_hpt_frequency);
51} 51}
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
new file mode 100644
index 000000000000..b93ed83474ec
--- /dev/null
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -0,0 +1,2 @@
1obj-y += setup.o platform.o nlm_hal.o
2obj-$(CONFIG_SMP) += wakeup.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
new file mode 100644
index 000000000000..9428e7125fed
--- /dev/null
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/kernel.h>
37#include <linux/mm.h>
38#include <linux/delay.h>
39
40#include <asm/mipsregs.h>
41#include <asm/time.h>
42
43#include <asm/netlogic/haldefs.h>
44#include <asm/netlogic/xlp-hal/iomap.h>
45#include <asm/netlogic/xlp-hal/xlp.h>
46#include <asm/netlogic/xlp-hal/pic.h>
47#include <asm/netlogic/xlp-hal/sys.h>
48
49/* These addresses are computed by the nlm_hal_init() */
50uint64_t nlm_io_base;
51uint64_t nlm_sys_base;
52uint64_t nlm_pic_base;
53
54/* Main initialization */
55void nlm_hal_init(void)
56{
57 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
58 nlm_sys_base = nlm_get_sys_regbase(0); /* node 0 */
59 nlm_pic_base = nlm_get_pic_regbase(0); /* node 0 */
60}
61
62int nlm_irq_to_irt(int irq)
63{
64 if (!PIC_IRQ_IS_IRT(irq))
65 return -1;
66
67 switch (irq) {
68 case PIC_UART_0_IRQ:
69 return PIC_IRT_UART_0_INDEX;
70 case PIC_UART_1_IRQ:
71 return PIC_IRT_UART_1_INDEX;
72 default:
73 return -1;
74 }
75}
76
77int nlm_irt_to_irq(int irt)
78{
79 switch (irt) {
80 case PIC_IRT_UART_0_INDEX:
81 return PIC_UART_0_IRQ;
82 case PIC_IRT_UART_1_INDEX:
83 return PIC_UART_1_IRQ;
84 default:
85 return -1;
86 }
87}
88
89unsigned int nlm_get_core_frequency(int core)
90{
91 unsigned int pll_divf, pll_divr, dfs_div, ext_div;
92 unsigned int rstval, dfsval, denom;
93 uint64_t num;
94
95 rstval = nlm_read_sys_reg(nlm_sys_base, SYS_POWER_ON_RESET_CFG);
96 dfsval = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIV_VALUE);
97 pll_divf = ((rstval >> 10) & 0x7f) + 1;
98 pll_divr = ((rstval >> 8) & 0x3) + 1;
99 ext_div = ((rstval >> 30) & 0x3) + 1;
100 dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
101
102 num = 800000000ULL * pll_divf;
103 denom = 3 * pll_divr * ext_div * dfs_div;
104 do_div(num, denom);
105 return (unsigned int)num;
106}
107
108unsigned int nlm_get_cpu_frequency(void)
109{
110 return nlm_get_core_frequency(0);
111}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
new file mode 100644
index 000000000000..1f5e4cba891d
--- /dev/null
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/dma-mapping.h>
36#include <linux/kernel.h>
37#include <linux/delay.h>
38#include <linux/init.h>
39#include <linux/platform_device.h>
40#include <linux/serial.h>
41#include <linux/serial_8250.h>
42#include <linux/pci.h>
43#include <linux/serial_reg.h>
44#include <linux/spinlock.h>
45
46#include <asm/time.h>
47#include <asm/addrspace.h>
48#include <asm/netlogic/haldefs.h>
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#include <asm/netlogic/xlp-hal/uart.h>
53
54static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
55{
56 return nlm_read_reg(p->iobase, offset);
57}
58
59static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
60{
61 nlm_write_reg(p->iobase, offset, value);
62}
63
64#define PORT(_irq) \
65 { \
66 .irq = _irq, \
67 .regshift = 2, \
68 .iotype = UPIO_MEM32, \
69 .flags = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\
70 UPF_BOOT_AUTOCONF), \
71 .uartclk = XLP_IO_CLK, \
72 .type = PORT_16550A, \
73 .serial_in = nlm_xlp_uart_in, \
74 .serial_out = nlm_xlp_uart_out, \
75 }
76
77static struct plat_serial8250_port xlp_uart_data[] = {
78 PORT(PIC_UART_0_IRQ),
79 PORT(PIC_UART_1_IRQ),
80 {},
81};
82
83static struct platform_device uart_device = {
84 .name = "serial8250",
85 .id = PLAT8250_DEV_PLATFORM,
86 .dev = {
87 .platform_data = xlp_uart_data,
88 },
89};
90
91static int __init nlm_platform_uart_init(void)
92{
93 unsigned long mmio;
94
95 mmio = (unsigned long)nlm_get_uart_regbase(0, 0);
96 xlp_uart_data[0].iobase = mmio;
97 xlp_uart_data[0].membase = (void __iomem *)mmio;
98 xlp_uart_data[0].mapbase = mmio;
99
100 mmio = (unsigned long)nlm_get_uart_regbase(0, 1);
101 xlp_uart_data[1].iobase = mmio;
102 xlp_uart_data[1].membase = (void __iomem *)mmio;
103 xlp_uart_data[1].mapbase = mmio;
104
105 return platform_device_register(&uart_device);
106}
107
108arch_initcall(nlm_platform_uart_init);
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
new file mode 100644
index 000000000000..acb677a1227c
--- /dev/null
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/serial_8250.h>
37#include <linux/pm.h>
38
39#include <asm/reboot.h>
40#include <asm/time.h>
41#include <asm/bootinfo.h>
42
43#include <linux/of_fdt.h>
44
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47
48#include <asm/netlogic/xlp-hal/iomap.h>
49#include <asm/netlogic/xlp-hal/xlp.h>
50#include <asm/netlogic/xlp-hal/sys.h>
51
52unsigned long nlm_common_ebase = 0x0;
53
54/* default to uniprocessor */
55uint32_t nlm_coremask = 1, nlm_cpumask = 1;
56int nlm_threads_per_core = 1;
57
58static void nlm_linux_exit(void)
59{
60 nlm_write_sys_reg(nlm_sys_base, SYS_CHIP_RESET, 1);
61 for ( ; ; )
62 cpu_wait();
63}
64
65void __init plat_mem_setup(void)
66{
67 panic_timeout = 5;
68 _machine_restart = (void (*)(char *))nlm_linux_exit;
69 _machine_halt = nlm_linux_exit;
70 pm_power_off = nlm_linux_exit;
71}
72
73const char *get_system_type(void)
74{
75 return "Netlogic XLP Series";
76}
77
78void __init prom_free_prom_memory(void)
79{
80 /* Nothing yet */
81}
82
83void xlp_mmu_init(void)
84{
85 write_c0_config6(read_c0_config6() | 0x24);
86 current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
87 write_c0_config7(PM_DEFAULT_MASK >>
88 (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
89}
90
91void __init prom_init(void)
92{
93 void *fdtp;
94
95 fdtp = (void *)(long)fw_arg0;
96 xlp_mmu_init();
97 nlm_hal_init();
98 early_init_devtree(fdtp);
99
100 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
101#ifdef CONFIG_SMP
102 nlm_wakeup_secondary_cpus(0xffffffff);
103 register_smp_ops(&nlm_smp_ops);
104#endif
105}
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
new file mode 100644
index 000000000000..44d923ff3846
--- /dev/null
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -0,0 +1,102 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36#include <linux/kernel.h>
37#include <linux/threads.h>
38
39#include <asm/asm.h>
40#include <asm/asm-offsets.h>
41#include <asm/mipsregs.h>
42#include <asm/addrspace.h>
43#include <asm/string.h>
44
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47#include <asm/netlogic/mips-extns.h>
48
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/pic.h>
51#include <asm/netlogic/xlp-hal/xlp.h>
52#include <asm/netlogic/xlp-hal/sys.h>
53
54static void xlp_enable_secondary_cores(void)
55{
56 uint32_t core, value, coremask, syscoremask;
57 int count;
58
59 /* read cores in reset from SYS block */
60 syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
61
62 /* update user specified */
63 nlm_coremask = nlm_coremask & (syscoremask | 1);
64
65 for (core = 1; core < 8; core++) {
66 coremask = 1 << core;
67 if ((nlm_coremask & coremask) == 0)
68 continue;
69
70 /* Enable CPU clock */
71 value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
72 value &= ~coremask;
73 nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
74
75 /* Remove CPU Reset */
76 value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
77 value &= ~coremask;
78 nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
79
80 /* Poll for CPU to mark itself coherent */
81 count = 100000;
82 do {
83 value = nlm_read_sys_reg(nlm_sys_base,
84 SYS_CPU_NONCOHERENT_MODE);
85 } while ((value & coremask) != 0 && count-- > 0);
86
87 if (count == 0)
88 pr_err("Failed to enable core %d\n", core);
89 }
90}
91
92void xlp_wakeup_secondary_cpus(void)
93{
94 /*
95 * In case of u-boot, the secondaries are in reset
96 * first wakeup core 0 threads
97 */
98 xlp_boot_core0_siblings();
99
100 /* now get other cores out of reset */
101 xlp_enable_secondary_cores();
102}
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index 2dca585dd2f7..f01e4d7a0600 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,5 +1,2 @@
1obj-y += setup.o platform.o irq.o setup.o time.o 1obj-y += setup.o platform.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o 2obj-$(CONFIG_SMP) += wakeup.o
3obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
4
5ccflags-y += -Werror
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
deleted file mode 100644
index 521bb7377eb0..000000000000
--- a/arch/mips/netlogic/xlr/irq.c
+++ /dev/null
@@ -1,300 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41
42#include <asm/mipsregs.h>
43
44#include <asm/netlogic/xlr/iomap.h>
45#include <asm/netlogic/xlr/pic.h>
46#include <asm/netlogic/xlr/xlr.h>
47
48#include <asm/netlogic/interrupt.h>
49#include <asm/netlogic/mips-extns.h>
50
51static u64 nlm_irq_mask;
52static DEFINE_SPINLOCK(nlm_pic_lock);
53
54static void xlr_pic_enable(struct irq_data *d)
55{
56 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
57 unsigned long flags;
58 nlm_reg_t reg;
59 int irq = d->irq;
60
61 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
62
63 spin_lock_irqsave(&nlm_pic_lock, flags);
64 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
65 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
66 reg | (1 << 6) | (1 << 30) | (1 << 31));
67 spin_unlock_irqrestore(&nlm_pic_lock, flags);
68}
69
70static void xlr_pic_mask(struct irq_data *d)
71{
72 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
73 unsigned long flags;
74 nlm_reg_t reg;
75 int irq = d->irq;
76
77 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
78
79 spin_lock_irqsave(&nlm_pic_lock, flags);
80 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
81 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
82 reg | (1 << 6) | (1 << 30) | (0 << 31));
83 spin_unlock_irqrestore(&nlm_pic_lock, flags);
84}
85
86#ifdef CONFIG_PCI
87/* Extra ACK needed for XLR on chip PCI controller */
88static void xlr_pci_ack(struct irq_data *d)
89{
90 nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
91
92 netlogic_read_reg(pci_mmio, (0x140 >> 2));
93}
94
95/* Extra ACK needed for XLS on chip PCIe controller */
96static void xls_pcie_ack(struct irq_data *d)
97{
98 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
99
100 switch (d->irq) {
101 case PIC_PCIE_LINK0_IRQ:
102 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
103 break;
104 case PIC_PCIE_LINK1_IRQ:
105 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
106 break;
107 case PIC_PCIE_LINK2_IRQ:
108 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
109 break;
110 case PIC_PCIE_LINK3_IRQ:
111 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
112 break;
113 }
114}
115
116/* For XLS B silicon, the 3,4 PCI interrupts are different */
117static void xls_pcie_ack_b(struct irq_data *d)
118{
119 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
120
121 switch (d->irq) {
122 case PIC_PCIE_LINK0_IRQ:
123 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
124 break;
125 case PIC_PCIE_LINK1_IRQ:
126 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
127 break;
128 case PIC_PCIE_XLSB0_LINK2_IRQ:
129 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
130 break;
131 case PIC_PCIE_XLSB0_LINK3_IRQ:
132 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
133 break;
134 }
135}
136#endif
137
138static void xlr_pic_ack(struct irq_data *d)
139{
140 unsigned long flags;
141 nlm_reg_t *mmio;
142 int irq = d->irq;
143 void *hd = irq_data_get_irq_handler_data(d);
144
145 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
146
147 if (hd) {
148 void (*extra_ack)(void *) = hd;
149 extra_ack(d);
150 }
151 mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
152 spin_lock_irqsave(&nlm_pic_lock, flags);
153 netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
154 spin_unlock_irqrestore(&nlm_pic_lock, flags);
155}
156
157/*
158 * This chip definition handles interrupts routed thru the XLR
159 * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
160 * 0-31 wired the XLR PIC
161 */
162static struct irq_chip xlr_pic = {
163 .name = "XLR-PIC",
164 .irq_enable = xlr_pic_enable,
165 .irq_mask = xlr_pic_mask,
166 .irq_ack = xlr_pic_ack,
167};
168
169static void rsvd_irq_handler(struct irq_data *d)
170{
171 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
172}
173
174/*
175 * Chip definition for CPU originated interrupts(timer, msg) and
176 * IPIs
177 */
178struct irq_chip nlm_cpu_intr = {
179 .name = "XLR-CPU-INTR",
180 .irq_enable = rsvd_irq_handler,
181 .irq_mask = rsvd_irq_handler,
182 .irq_ack = rsvd_irq_handler,
183};
184
185void __init init_xlr_irqs(void)
186{
187 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
188 uint32_t thread_mask = 1;
189 int level, i;
190
191 pr_info("Interrupt thread mask [%x]\n", thread_mask);
192 for (i = 0; i < PIC_NUM_IRTS; i++) {
193 level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
194
195 /* Bind all PIC irqs to boot cpu */
196 netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
197
198 /*
199 * Use local scheduling and high polarity for all IRTs
200 * Invalidate all IRTs, by default
201 */
202 netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
203 (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
204 }
205
206 /* Make all IRQs as level triggered by default */
207 for (i = 0; i < NR_IRQS; i++) {
208 if (PIC_IRQ_IS_IRT(i))
209 irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
210 else
211 irq_set_chip_and_handler(i, &nlm_cpu_intr,
212 handle_percpu_irq);
213 }
214#ifdef CONFIG_SMP
215 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
216 nlm_smp_function_ipi_handler);
217 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
218 nlm_smp_resched_ipi_handler);
219 nlm_irq_mask |=
220 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
221#endif
222
223#ifdef CONFIG_PCI
224 /*
225 * For PCI interrupts, we need to ack the PIC controller too, overload
226 * irq handler data to do this
227 */
228 if (nlm_chip_is_xls()) {
229 if (nlm_chip_is_xls_b()) {
230 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
231 xls_pcie_ack_b);
232 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
233 xls_pcie_ack_b);
234 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
235 xls_pcie_ack_b);
236 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
237 xls_pcie_ack_b);
238 } else {
239 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
240 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
241 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
242 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
243 }
244 } else {
245 /* XLR PCI controller ACK */
246 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
247 }
248#endif
249 /* unmask all PIC related interrupts. If no handler is installed by the
250 * drivers, it'll just ack the interrupt and return
251 */
252 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
253 nlm_irq_mask |= (1ULL << i);
254
255 nlm_irq_mask |= (1ULL << IRQ_TIMER);
256}
257
258void __init arch_init_irq(void)
259{
260 /* Initialize the irq descriptors */
261 init_xlr_irqs();
262 write_c0_eimr(nlm_irq_mask);
263}
264
265void __cpuinit nlm_smp_irq_init(void)
266{
267 /* set interrupt mask for non-zero cpus */
268 write_c0_eimr(nlm_irq_mask);
269}
270
271asmlinkage void plat_irq_dispatch(void)
272{
273 uint64_t eirr;
274 int i;
275
276 eirr = read_c0_eirr() & read_c0_eimr();
277 if (!eirr)
278 return;
279
280 /* no need of EIRR here, writing compare clears interrupt */
281 if (eirr & (1 << IRQ_TIMER)) {
282 do_IRQ(IRQ_TIMER);
283 return;
284 }
285
286 /* use dcltz: optimize below code */
287 for (i = 63; i != -1; i--) {
288 if (eirr & (1ULL << i))
289 break;
290 }
291 if (i == -1) {
292 pr_err("no interrupt !!\n");
293 return;
294 }
295
296 /* Ack eirr */
297 write_c0_eirr(1ULL << i);
298
299 do_IRQ(i);
300}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 609ec2534642..eab64b45dffd 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -15,18 +15,19 @@
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17 17
18#include <asm/netlogic/haldefs.h>
18#include <asm/netlogic/xlr/iomap.h> 19#include <asm/netlogic/xlr/iomap.h>
19#include <asm/netlogic/xlr/pic.h> 20#include <asm/netlogic/xlr/pic.h>
20#include <asm/netlogic/xlr/xlr.h> 21#include <asm/netlogic/xlr/xlr.h>
21 22
22unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 23unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
23{ 24{
24 nlm_reg_t *mmio; 25 uint64_t uartbase;
25 unsigned int value; 26 unsigned int value;
26 27
27 /* XLR uart does not need any mapping of regs */ 28 /* sign extend to 64 bits, if needed */
28 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 29 uartbase = (uint64_t)(long)p->membase;
29 value = netlogic_read_reg(mmio, 0); 30 value = nlm_read_reg(uartbase, offset);
30 31
31 /* See XLR/XLS errata */ 32 /* See XLR/XLS errata */
32 if (offset == UART_MSR) 33 if (offset == UART_MSR)
@@ -39,10 +40,10 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
39 40
40void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 41void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
41{ 42{
42 nlm_reg_t *mmio; 43 uint64_t uartbase;
43 44
44 /* XLR uart does not need any mapping of regs */ 45 /* sign extend to 64 bits, if needed */
45 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 46 uartbase = (uint64_t)(long)p->membase;
46 47
47 /* See XLR/XLS errata */ 48 /* See XLR/XLS errata */
48 if (offset == UART_MSR) 49 if (offset == UART_MSR)
@@ -50,7 +51,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
50 else if (offset == UART_MCR) 51 else if (offset == UART_MCR)
51 value ^= 0x3; 52 value ^= 0x3;
52 53
53 netlogic_write_reg(mmio, 0, value); 54 nlm_write_reg(uartbase, offset, value);
54} 55}
55 56
56#define PORT(_irq) \ 57#define PORT(_irq) \
@@ -82,15 +83,15 @@ static struct platform_device uart_device = {
82 83
83static int __init nlm_uart_init(void) 84static int __init nlm_uart_init(void)
84{ 85{
85 nlm_reg_t *mmio; 86 unsigned long uartbase;
86 87
87 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 88 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
88 xlr_uart_data[0].membase = (void __iomem *)mmio; 89 xlr_uart_data[0].membase = (void __iomem *)uartbase;
89 xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio); 90 xlr_uart_data[0].mapbase = CPHYSADDR(uartbase);
90 91
91 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); 92 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET);
92 xlr_uart_data[1].membase = (void __iomem *)mmio; 93 xlr_uart_data[1].membase = (void __iomem *)uartbase;
93 xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio); 94 xlr_uart_data[1].mapbase = CPHYSADDR(uartbase);
94 95
95 return platform_device_register(&uart_device); 96 return platform_device_register(&uart_device);
96} 97}
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index cee25ddd0887..c9d066dedc4e 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -39,26 +39,33 @@
39#include <asm/reboot.h> 39#include <asm/reboot.h>
40#include <asm/time.h> 40#include <asm/time.h>
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42#include <asm/smp-ops.h>
43 42
44#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/psb-bootinfo.h> 44#include <asm/netlogic/psb-bootinfo.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
46 47
47#include <asm/netlogic/xlr/xlr.h> 48#include <asm/netlogic/xlr/xlr.h>
48#include <asm/netlogic/xlr/iomap.h> 49#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h> 50#include <asm/netlogic/xlr/pic.h>
50#include <asm/netlogic/xlr/gpio.h> 51#include <asm/netlogic/xlr/gpio.h>
51 52
52unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); 53uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
53unsigned long nlm_common_ebase = 0x0; 54uint64_t nlm_pic_base;
54struct psb_info nlm_prom_info; 55struct psb_info nlm_prom_info;
55 56
57unsigned long nlm_common_ebase = 0x0;
58
59/* default to uniprocessor */
60uint32_t nlm_coremask = 1, nlm_cpumask = 1;
61int nlm_threads_per_core = 1;
62
56static void __init nlm_early_serial_setup(void) 63static void __init nlm_early_serial_setup(void)
57{ 64{
58 struct uart_port s; 65 struct uart_port s;
59 nlm_reg_t *uart_base; 66 unsigned long uart_base;
60 67
61 uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 68 uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
62 memset(&s, 0, sizeof(s)); 69 memset(&s, 0, sizeof(s));
63 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; 70 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
64 s.iotype = UPIO_MEM32; 71 s.iotype = UPIO_MEM32;
@@ -67,18 +74,18 @@ static void __init nlm_early_serial_setup(void)
67 s.uartclk = PIC_CLKS_PER_SEC; 74 s.uartclk = PIC_CLKS_PER_SEC;
68 s.serial_in = nlm_xlr_uart_in; 75 s.serial_in = nlm_xlr_uart_in;
69 s.serial_out = nlm_xlr_uart_out; 76 s.serial_out = nlm_xlr_uart_out;
70 s.mapbase = (unsigned long)uart_base; 77 s.mapbase = uart_base;
71 s.membase = (unsigned char __iomem *)uart_base; 78 s.membase = (unsigned char __iomem *)uart_base;
72 early_serial_setup(&s); 79 early_serial_setup(&s);
73} 80}
74 81
75static void nlm_linux_exit(void) 82static void nlm_linux_exit(void)
76{ 83{
77 nlm_reg_t *mmio; 84 uint64_t gpiobase;
78 85
79 mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); 86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
80 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ 87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
81 netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); 88 nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
82 for ( ; ; ) 89 for ( ; ; )
83 cpu_wait(); 90 cpu_wait();
84} 91}
@@ -96,6 +103,11 @@ const char *get_system_type(void)
96 return "Netlogic XLR/XLS Series"; 103 return "Netlogic XLR/XLS Series";
97} 104}
98 105
106unsigned int nlm_get_cpu_frequency(void)
107{
108 return (unsigned int)nlm_prom_info.cpu_frequency;
109}
110
99void __init prom_free_prom_memory(void) 111void __init prom_free_prom_memory(void)
100{ 112{
101 /* Nothing yet */ 113 /* Nothing yet */
@@ -175,6 +187,7 @@ void __init prom_init(void)
175 prom_infop = (struct psb_info *)(long)(int)fw_arg3; 187 prom_infop = (struct psb_info *)(long)(int)fw_arg3;
176 188
177 nlm_prom_info = *prom_infop; 189 nlm_prom_info = *prom_infop;
190 nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
178 191
179 nlm_early_serial_setup(); 192 nlm_early_serial_setup();
180 build_arcs_cmdline(argv); 193 build_arcs_cmdline(argv);
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/wakeup.c
index 8cb7889ce0cc..db5d987d4881 100644
--- a/arch/mips/netlogic/xlr/smpboot.S
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -33,68 +33,36 @@
33 */ 33 */
34 34
35#include <linux/init.h> 35#include <linux/init.h>
36#include <linux/threads.h>
36 37
37#include <asm/asm.h> 38#include <asm/asm.h>
38#include <asm/asm-offsets.h> 39#include <asm/asm-offsets.h>
39#include <asm/regdef.h>
40#include <asm/mipsregs.h> 40#include <asm/mipsregs.h>
41#include <asm/addrspace.h>
42#include <asm/string.h>
41 43
42/* 44#include <asm/netlogic/haldefs.h>
43 * Early code for secondary CPUs. This will get them out of the bootloader 45#include <asm/netlogic/common.h>
44 * code and into linux. Needed because the bootloader area will be taken 46#include <asm/netlogic/mips-extns.h>
45 * and initialized by linux.
46 */
47 __CPUINIT
48NESTED(prom_pre_boot_secondary_cpus, 16, sp)
49 .set mips64
50 mfc0 t0, $15, 1 # read ebase
51 andi t0, 0x1f # t0 has the processor_id()
52 sll t0, 2 # offset in cpu array
53
54 PTR_LA t1, nlm_cpu_ready # mark CPU ready
55 PTR_ADDU t1, t0
56 li t2, 1
57 sw t2, 0(t1)
58
59 PTR_LA t1, nlm_cpu_unblock
60 PTR_ADDU t1, t0
611: lw t2, 0(t1) # wait till unblocked
62 beqz t2, 1b
63 nop
64 47
65 PTR_LA t1, nlm_next_sp 48#include <asm/netlogic/xlr/iomap.h>
66 PTR_L sp, 0(t1) 49#include <asm/netlogic/xlr/pic.h>
67 PTR_LA t1, nlm_next_gp
68 PTR_L gp, 0(t1)
69 50
70 PTR_LA t0, nlm_early_init_secondary 51int __cpuinit xlr_wakeup_secondary_cpus(void)
71 jalr t0 52{
72 nop 53 unsigned int i, boot_cpu;
73
74 PTR_LA t0, smp_bootstrap
75 jr t0
76 nop
77END(prom_pre_boot_secondary_cpus)
78 __FINIT
79
80/*
81 * NMI code, used for CPU wakeup, copied to reset entry
82 */
83NESTED(nlm_boot_smp_nmi, 0, sp)
84 .set push
85 .set noat
86 .set mips64
87 .set noreorder
88 54
89 /* Clear the NMI and BEV bits */ 55 /*
90 MFC0 k0, CP0_STATUS 56 * In case of RMI boot, hit with NMI to get the cores
91 li k1, 0xffb7ffff 57 * from bootloader to linux code.
92 and k0, k0, k1 58 */
93 MTC0 k0, CP0_STATUS 59 boot_cpu = hard_smp_processor_id();
60 nlm_set_nmi_handler(nlm_rmiboot_preboot);
61 for (i = 0; i < NR_CPUS; i++) {
62 if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
63 continue;
64 nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
65 }
94 66
95 PTR_LA k1, secondary_entry_point 67 return 0;
96 PTR_L k0, 0(k1) 68}
97 jr k0
98 nop
99 .set pop
100END(nlm_boot_smp_nmi)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 09:09:41 -0500