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-rw-r--r--arch/mips/netlogic/xlr/Makefile7
-rw-r--r--arch/mips/netlogic/xlr/irq.c300
-rw-r--r--arch/mips/netlogic/xlr/platform.c31
-rw-r--r--arch/mips/netlogic/xlr/setup.c31
-rw-r--r--arch/mips/netlogic/xlr/smp.c220
-rw-r--r--arch/mips/netlogic/xlr/smpboot.S100
-rw-r--r--arch/mips/netlogic/xlr/time.c51
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c (renamed from arch/mips/netlogic/xlr/xlr_console.c)36
8 files changed, 69 insertions, 707 deletions
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index 2dca585dd2f7..f01e4d7a0600 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,5 +1,2 @@
1obj-y += setup.o platform.o irq.o setup.o time.o 1obj-y += setup.o platform.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o 2obj-$(CONFIG_SMP) += wakeup.o
3obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
4
5ccflags-y += -Werror
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
deleted file mode 100644
index 521bb7377eb0..000000000000
--- a/arch/mips/netlogic/xlr/irq.c
+++ /dev/null
@@ -1,300 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41
42#include <asm/mipsregs.h>
43
44#include <asm/netlogic/xlr/iomap.h>
45#include <asm/netlogic/xlr/pic.h>
46#include <asm/netlogic/xlr/xlr.h>
47
48#include <asm/netlogic/interrupt.h>
49#include <asm/netlogic/mips-extns.h>
50
51static u64 nlm_irq_mask;
52static DEFINE_SPINLOCK(nlm_pic_lock);
53
54static void xlr_pic_enable(struct irq_data *d)
55{
56 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
57 unsigned long flags;
58 nlm_reg_t reg;
59 int irq = d->irq;
60
61 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
62
63 spin_lock_irqsave(&nlm_pic_lock, flags);
64 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
65 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
66 reg | (1 << 6) | (1 << 30) | (1 << 31));
67 spin_unlock_irqrestore(&nlm_pic_lock, flags);
68}
69
70static void xlr_pic_mask(struct irq_data *d)
71{
72 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
73 unsigned long flags;
74 nlm_reg_t reg;
75 int irq = d->irq;
76
77 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
78
79 spin_lock_irqsave(&nlm_pic_lock, flags);
80 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
81 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
82 reg | (1 << 6) | (1 << 30) | (0 << 31));
83 spin_unlock_irqrestore(&nlm_pic_lock, flags);
84}
85
86#ifdef CONFIG_PCI
87/* Extra ACK needed for XLR on chip PCI controller */
88static void xlr_pci_ack(struct irq_data *d)
89{
90 nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
91
92 netlogic_read_reg(pci_mmio, (0x140 >> 2));
93}
94
95/* Extra ACK needed for XLS on chip PCIe controller */
96static void xls_pcie_ack(struct irq_data *d)
97{
98 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
99
100 switch (d->irq) {
101 case PIC_PCIE_LINK0_IRQ:
102 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
103 break;
104 case PIC_PCIE_LINK1_IRQ:
105 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
106 break;
107 case PIC_PCIE_LINK2_IRQ:
108 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
109 break;
110 case PIC_PCIE_LINK3_IRQ:
111 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
112 break;
113 }
114}
115
116/* For XLS B silicon, the 3,4 PCI interrupts are different */
117static void xls_pcie_ack_b(struct irq_data *d)
118{
119 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
120
121 switch (d->irq) {
122 case PIC_PCIE_LINK0_IRQ:
123 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
124 break;
125 case PIC_PCIE_LINK1_IRQ:
126 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
127 break;
128 case PIC_PCIE_XLSB0_LINK2_IRQ:
129 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
130 break;
131 case PIC_PCIE_XLSB0_LINK3_IRQ:
132 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
133 break;
134 }
135}
136#endif
137
138static void xlr_pic_ack(struct irq_data *d)
139{
140 unsigned long flags;
141 nlm_reg_t *mmio;
142 int irq = d->irq;
143 void *hd = irq_data_get_irq_handler_data(d);
144
145 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
146
147 if (hd) {
148 void (*extra_ack)(void *) = hd;
149 extra_ack(d);
150 }
151 mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
152 spin_lock_irqsave(&nlm_pic_lock, flags);
153 netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
154 spin_unlock_irqrestore(&nlm_pic_lock, flags);
155}
156
157/*
158 * This chip definition handles interrupts routed thru the XLR
159 * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
160 * 0-31 wired the XLR PIC
161 */
162static struct irq_chip xlr_pic = {
163 .name = "XLR-PIC",
164 .irq_enable = xlr_pic_enable,
165 .irq_mask = xlr_pic_mask,
166 .irq_ack = xlr_pic_ack,
167};
168
169static void rsvd_irq_handler(struct irq_data *d)
170{
171 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
172}
173
174/*
175 * Chip definition for CPU originated interrupts(timer, msg) and
176 * IPIs
177 */
178struct irq_chip nlm_cpu_intr = {
179 .name = "XLR-CPU-INTR",
180 .irq_enable = rsvd_irq_handler,
181 .irq_mask = rsvd_irq_handler,
182 .irq_ack = rsvd_irq_handler,
183};
184
185void __init init_xlr_irqs(void)
186{
187 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
188 uint32_t thread_mask = 1;
189 int level, i;
190
191 pr_info("Interrupt thread mask [%x]\n", thread_mask);
192 for (i = 0; i < PIC_NUM_IRTS; i++) {
193 level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
194
195 /* Bind all PIC irqs to boot cpu */
196 netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
197
198 /*
199 * Use local scheduling and high polarity for all IRTs
200 * Invalidate all IRTs, by default
201 */
202 netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
203 (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
204 }
205
206 /* Make all IRQs as level triggered by default */
207 for (i = 0; i < NR_IRQS; i++) {
208 if (PIC_IRQ_IS_IRT(i))
209 irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
210 else
211 irq_set_chip_and_handler(i, &nlm_cpu_intr,
212 handle_percpu_irq);
213 }
214#ifdef CONFIG_SMP
215 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
216 nlm_smp_function_ipi_handler);
217 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
218 nlm_smp_resched_ipi_handler);
219 nlm_irq_mask |=
220 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
221#endif
222
223#ifdef CONFIG_PCI
224 /*
225 * For PCI interrupts, we need to ack the PIC controller too, overload
226 * irq handler data to do this
227 */
228 if (nlm_chip_is_xls()) {
229 if (nlm_chip_is_xls_b()) {
230 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
231 xls_pcie_ack_b);
232 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
233 xls_pcie_ack_b);
234 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
235 xls_pcie_ack_b);
236 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
237 xls_pcie_ack_b);
238 } else {
239 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
240 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
241 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
242 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
243 }
244 } else {
245 /* XLR PCI controller ACK */
246 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
247 }
248#endif
249 /* unmask all PIC related interrupts. If no handler is installed by the
250 * drivers, it'll just ack the interrupt and return
251 */
252 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
253 nlm_irq_mask |= (1ULL << i);
254
255 nlm_irq_mask |= (1ULL << IRQ_TIMER);
256}
257
258void __init arch_init_irq(void)
259{
260 /* Initialize the irq descriptors */
261 init_xlr_irqs();
262 write_c0_eimr(nlm_irq_mask);
263}
264
265void __cpuinit nlm_smp_irq_init(void)
266{
267 /* set interrupt mask for non-zero cpus */
268 write_c0_eimr(nlm_irq_mask);
269}
270
271asmlinkage void plat_irq_dispatch(void)
272{
273 uint64_t eirr;
274 int i;
275
276 eirr = read_c0_eirr() & read_c0_eimr();
277 if (!eirr)
278 return;
279
280 /* no need of EIRR here, writing compare clears interrupt */
281 if (eirr & (1 << IRQ_TIMER)) {
282 do_IRQ(IRQ_TIMER);
283 return;
284 }
285
286 /* use dcltz: optimize below code */
287 for (i = 63; i != -1; i--) {
288 if (eirr & (1ULL << i))
289 break;
290 }
291 if (i == -1) {
292 pr_err("no interrupt !!\n");
293 return;
294 }
295
296 /* Ack eirr */
297 write_c0_eirr(1ULL << i);
298
299 do_IRQ(i);
300}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 609ec2534642..eab64b45dffd 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -15,18 +15,19 @@
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17 17
18#include <asm/netlogic/haldefs.h>
18#include <asm/netlogic/xlr/iomap.h> 19#include <asm/netlogic/xlr/iomap.h>
19#include <asm/netlogic/xlr/pic.h> 20#include <asm/netlogic/xlr/pic.h>
20#include <asm/netlogic/xlr/xlr.h> 21#include <asm/netlogic/xlr/xlr.h>
21 22
22unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 23unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
23{ 24{
24 nlm_reg_t *mmio; 25 uint64_t uartbase;
25 unsigned int value; 26 unsigned int value;
26 27
27 /* XLR uart does not need any mapping of regs */ 28 /* sign extend to 64 bits, if needed */
28 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 29 uartbase = (uint64_t)(long)p->membase;
29 value = netlogic_read_reg(mmio, 0); 30 value = nlm_read_reg(uartbase, offset);
30 31
31 /* See XLR/XLS errata */ 32 /* See XLR/XLS errata */
32 if (offset == UART_MSR) 33 if (offset == UART_MSR)
@@ -39,10 +40,10 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
39 40
40void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 41void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
41{ 42{
42 nlm_reg_t *mmio; 43 uint64_t uartbase;
43 44
44 /* XLR uart does not need any mapping of regs */ 45 /* sign extend to 64 bits, if needed */
45 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 46 uartbase = (uint64_t)(long)p->membase;
46 47
47 /* See XLR/XLS errata */ 48 /* See XLR/XLS errata */
48 if (offset == UART_MSR) 49 if (offset == UART_MSR)
@@ -50,7 +51,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
50 else if (offset == UART_MCR) 51 else if (offset == UART_MCR)
51 value ^= 0x3; 52 value ^= 0x3;
52 53
53 netlogic_write_reg(mmio, 0, value); 54 nlm_write_reg(uartbase, offset, value);
54} 55}
55 56
56#define PORT(_irq) \ 57#define PORT(_irq) \
@@ -82,15 +83,15 @@ static struct platform_device uart_device = {
82 83
83static int __init nlm_uart_init(void) 84static int __init nlm_uart_init(void)
84{ 85{
85 nlm_reg_t *mmio; 86 unsigned long uartbase;
86 87
87 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 88 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
88 xlr_uart_data[0].membase = (void __iomem *)mmio; 89 xlr_uart_data[0].membase = (void __iomem *)uartbase;
89 xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio); 90 xlr_uart_data[0].mapbase = CPHYSADDR(uartbase);
90 91
91 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); 92 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET);
92 xlr_uart_data[1].membase = (void __iomem *)mmio; 93 xlr_uart_data[1].membase = (void __iomem *)uartbase;
93 xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio); 94 xlr_uart_data[1].mapbase = CPHYSADDR(uartbase);
94 95
95 return platform_device_register(&uart_device); 96 return platform_device_register(&uart_device);
96} 97}
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index cee25ddd0887..c9d066dedc4e 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -39,26 +39,33 @@
39#include <asm/reboot.h> 39#include <asm/reboot.h>
40#include <asm/time.h> 40#include <asm/time.h>
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42#include <asm/smp-ops.h>
43 42
44#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/psb-bootinfo.h> 44#include <asm/netlogic/psb-bootinfo.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
46 47
47#include <asm/netlogic/xlr/xlr.h> 48#include <asm/netlogic/xlr/xlr.h>
48#include <asm/netlogic/xlr/iomap.h> 49#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h> 50#include <asm/netlogic/xlr/pic.h>
50#include <asm/netlogic/xlr/gpio.h> 51#include <asm/netlogic/xlr/gpio.h>
51 52
52unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); 53uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
53unsigned long nlm_common_ebase = 0x0; 54uint64_t nlm_pic_base;
54struct psb_info nlm_prom_info; 55struct psb_info nlm_prom_info;
55 56
57unsigned long nlm_common_ebase = 0x0;
58
59/* default to uniprocessor */
60uint32_t nlm_coremask = 1, nlm_cpumask = 1;
61int nlm_threads_per_core = 1;
62
56static void __init nlm_early_serial_setup(void) 63static void __init nlm_early_serial_setup(void)
57{ 64{
58 struct uart_port s; 65 struct uart_port s;
59 nlm_reg_t *uart_base; 66 unsigned long uart_base;
60 67
61 uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 68 uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
62 memset(&s, 0, sizeof(s)); 69 memset(&s, 0, sizeof(s));
63 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; 70 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
64 s.iotype = UPIO_MEM32; 71 s.iotype = UPIO_MEM32;
@@ -67,18 +74,18 @@ static void __init nlm_early_serial_setup(void)
67 s.uartclk = PIC_CLKS_PER_SEC; 74 s.uartclk = PIC_CLKS_PER_SEC;
68 s.serial_in = nlm_xlr_uart_in; 75 s.serial_in = nlm_xlr_uart_in;
69 s.serial_out = nlm_xlr_uart_out; 76 s.serial_out = nlm_xlr_uart_out;
70 s.mapbase = (unsigned long)uart_base; 77 s.mapbase = uart_base;
71 s.membase = (unsigned char __iomem *)uart_base; 78 s.membase = (unsigned char __iomem *)uart_base;
72 early_serial_setup(&s); 79 early_serial_setup(&s);
73} 80}
74 81
75static void nlm_linux_exit(void) 82static void nlm_linux_exit(void)
76{ 83{
77 nlm_reg_t *mmio; 84 uint64_t gpiobase;
78 85
79 mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); 86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
80 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ 87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
81 netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); 88 nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
82 for ( ; ; ) 89 for ( ; ; )
83 cpu_wait(); 90 cpu_wait();
84} 91}
@@ -96,6 +103,11 @@ const char *get_system_type(void)
96 return "Netlogic XLR/XLS Series"; 103 return "Netlogic XLR/XLS Series";
97} 104}
98 105
106unsigned int nlm_get_cpu_frequency(void)
107{
108 return (unsigned int)nlm_prom_info.cpu_frequency;
109}
110
99void __init prom_free_prom_memory(void) 111void __init prom_free_prom_memory(void)
100{ 112{
101 /* Nothing yet */ 113 /* Nothing yet */
@@ -175,6 +187,7 @@ void __init prom_init(void)
175 prom_infop = (struct psb_info *)(long)(int)fw_arg3; 187 prom_infop = (struct psb_info *)(long)(int)fw_arg3;
176 188
177 nlm_prom_info = *prom_infop; 189 nlm_prom_info = *prom_infop;
190 nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
178 191
179 nlm_early_serial_setup(); 192 nlm_early_serial_setup();
180 build_arcs_cmdline(argv); 193 build_arcs_cmdline(argv);
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c
deleted file mode 100644
index 080284ded508..000000000000
--- a/arch/mips/netlogic/xlr/smp.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/delay.h>
37#include <linux/init.h>
38#include <linux/smp.h>
39#include <linux/irq.h>
40
41#include <asm/mmu_context.h>
42
43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h>
45
46#include <asm/netlogic/xlr/iomap.h>
47#include <asm/netlogic/xlr/pic.h>
48#include <asm/netlogic/xlr/xlr.h>
49
50void core_send_ipi(int logical_cpu, unsigned int action)
51{
52 int cpu = cpu_logical_map(logical_cpu);
53 u32 tid = cpu & 0x3;
54 u32 pid = (cpu >> 2) & 0x07;
55 u32 ipi = (tid << 16) | (pid << 20);
56
57 if (action & SMP_CALL_FUNCTION)
58 ipi |= IRQ_IPI_SMP_FUNCTION;
59 else if (action & SMP_RESCHEDULE_YOURSELF)
60 ipi |= IRQ_IPI_SMP_RESCHEDULE;
61 else
62 return;
63
64 pic_send_ipi(ipi);
65}
66
67void nlm_send_ipi_single(int cpu, unsigned int action)
68{
69 core_send_ipi(cpu, action);
70}
71
72void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
73{
74 int cpu;
75
76 for_each_cpu(cpu, mask) {
77 core_send_ipi(cpu, action);
78 }
79}
80
81/* IRQ_IPI_SMP_FUNCTION Handler */
82void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
83{
84 smp_call_function_interrupt();
85}
86
87/* IRQ_IPI_SMP_RESCHEDULE handler */
88void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
89{
90 scheduler_ipi();
91}
92
93/*
94 * Called before going into mips code, early cpu init
95 */
96void nlm_early_init_secondary(void)
97{
98 write_c0_ebase((uint32_t)nlm_common_ebase);
99 /* TLB partition here later */
100}
101
102/*
103 * Code to run on secondary just after probing the CPU
104 */
105static void __cpuinit nlm_init_secondary(void)
106{
107 nlm_smp_irq_init();
108}
109
110void nlm_smp_finish(void)
111{
112#ifdef notyet
113 nlm_common_msgring_cpu_init();
114#endif
115 local_irq_enable();
116}
117
118void nlm_cpus_done(void)
119{
120}
121
122/*
123 * Boot all other cpus in the system, initialize them, and bring them into
124 * the boot function
125 */
126int nlm_cpu_unblock[NR_CPUS];
127int nlm_cpu_ready[NR_CPUS];
128unsigned long nlm_next_gp;
129unsigned long nlm_next_sp;
130cpumask_t phys_cpu_present_map;
131
132void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
133{
134 unsigned long gp = (unsigned long)task_thread_info(idle);
135 unsigned long sp = (unsigned long)__KSTK_TOS(idle);
136 int cpu = cpu_logical_map(logical_cpu);
137
138 nlm_next_sp = sp;
139 nlm_next_gp = gp;
140
141 /* barrier */
142 __sync();
143 nlm_cpu_unblock[cpu] = 1;
144}
145
146void __init nlm_smp_setup(void)
147{
148 unsigned int boot_cpu;
149 int num_cpus, i;
150
151 boot_cpu = hard_smp_processor_id();
152 cpus_clear(phys_cpu_present_map);
153
154 cpu_set(boot_cpu, phys_cpu_present_map);
155 __cpu_number_map[boot_cpu] = 0;
156 __cpu_logical_map[0] = boot_cpu;
157 cpu_set(0, cpu_possible_map);
158
159 num_cpus = 1;
160 for (i = 0; i < NR_CPUS; i++) {
161 /*
162 * BSP is not set in nlm_cpu_ready array, it is only for
163 * ASPs (goto see smpboot.S)
164 */
165 if (nlm_cpu_ready[i]) {
166 cpu_set(i, phys_cpu_present_map);
167 __cpu_number_map[i] = num_cpus;
168 __cpu_logical_map[num_cpus] = i;
169 cpu_set(num_cpus, cpu_possible_map);
170 ++num_cpus;
171 }
172 }
173
174 pr_info("Phys CPU present map: %lx, possible map %lx\n",
175 (unsigned long)phys_cpu_present_map.bits[0],
176 (unsigned long)cpu_possible_map.bits[0]);
177
178 pr_info("Detected %i Slave CPU(s)\n", num_cpus);
179}
180
181void nlm_prepare_cpus(unsigned int max_cpus)
182{
183}
184
185struct plat_smp_ops nlm_smp_ops = {
186 .send_ipi_single = nlm_send_ipi_single,
187 .send_ipi_mask = nlm_send_ipi_mask,
188 .init_secondary = nlm_init_secondary,
189 .smp_finish = nlm_smp_finish,
190 .cpus_done = nlm_cpus_done,
191 .boot_secondary = nlm_boot_secondary,
192 .smp_setup = nlm_smp_setup,
193 .prepare_cpus = nlm_prepare_cpus,
194};
195
196unsigned long secondary_entry_point;
197
198int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
199{
200 unsigned int tid, pid, ipi, i, boot_cpu;
201 void *reset_vec;
202
203 secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
204 reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
205 memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
206 boot_cpu = hard_smp_processor_id();
207
208 for (i = 0; i < NR_CPUS; i++) {
209 if (i == boot_cpu)
210 continue;
211 if (wakeup_mask & (1u << i)) {
212 tid = i & 0x3;
213 pid = (i >> 2) & 0x7;
214 ipi = (tid << 16) | (pid << 20) | (1 << 8);
215 pic_send_ipi(ipi);
216 }
217 }
218
219 return 0;
220}
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S
deleted file mode 100644
index 8cb7889ce0cc..000000000000
--- a/arch/mips/netlogic/xlr/smpboot.S
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36
37#include <asm/asm.h>
38#include <asm/asm-offsets.h>
39#include <asm/regdef.h>
40#include <asm/mipsregs.h>
41
42/*
43 * Early code for secondary CPUs. This will get them out of the bootloader
44 * code and into linux. Needed because the bootloader area will be taken
45 * and initialized by linux.
46 */
47 __CPUINIT
48NESTED(prom_pre_boot_secondary_cpus, 16, sp)
49 .set mips64
50 mfc0 t0, $15, 1 # read ebase
51 andi t0, 0x1f # t0 has the processor_id()
52 sll t0, 2 # offset in cpu array
53
54 PTR_LA t1, nlm_cpu_ready # mark CPU ready
55 PTR_ADDU t1, t0
56 li t2, 1
57 sw t2, 0(t1)
58
59 PTR_LA t1, nlm_cpu_unblock
60 PTR_ADDU t1, t0
611: lw t2, 0(t1) # wait till unblocked
62 beqz t2, 1b
63 nop
64
65 PTR_LA t1, nlm_next_sp
66 PTR_L sp, 0(t1)
67 PTR_LA t1, nlm_next_gp
68 PTR_L gp, 0(t1)
69
70 PTR_LA t0, nlm_early_init_secondary
71 jalr t0
72 nop
73
74 PTR_LA t0, smp_bootstrap
75 jr t0
76 nop
77END(prom_pre_boot_secondary_cpus)
78 __FINIT
79
80/*
81 * NMI code, used for CPU wakeup, copied to reset entry
82 */
83NESTED(nlm_boot_smp_nmi, 0, sp)
84 .set push
85 .set noat
86 .set mips64
87 .set noreorder
88
89 /* Clear the NMI and BEV bits */
90 MFC0 k0, CP0_STATUS
91 li k1, 0xffb7ffff
92 and k0, k0, k1
93 MTC0 k0, CP0_STATUS
94
95 PTR_LA k1, secondary_entry_point
96 PTR_L k0, 0(k1)
97 jr k0
98 nop
99 .set pop
100END(nlm_boot_smp_nmi)
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c
deleted file mode 100644
index 0d81b262593c..000000000000
--- a/arch/mips/netlogic/xlr/time.c
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36
37#include <asm/time.h>
38#include <asm/netlogic/interrupt.h>
39#include <asm/netlogic/psb-bootinfo.h>
40
41unsigned int __cpuinit get_c0_compare_int(void)
42{
43 return IRQ_TIMER;
44}
45
46void __init plat_time_init(void)
47{
48 mips_hpt_frequency = nlm_prom_info.cpu_frequency;
49 pr_info("MIPS counter frequency [%ld]\n",
50 (unsigned long)mips_hpt_frequency);
51}
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/wakeup.c
index 759df0692201..db5d987d4881 100644
--- a/arch/mips/netlogic/xlr/xlr_console.c
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -32,15 +32,37 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/types.h> 35#include <linux/init.h>
36#include <linux/threads.h>
37
38#include <asm/asm.h>
39#include <asm/asm-offsets.h>
40#include <asm/mipsregs.h>
41#include <asm/addrspace.h>
42#include <asm/string.h>
43
44#include <asm/netlogic/haldefs.h>
45#include <asm/netlogic/common.h>
46#include <asm/netlogic/mips-extns.h>
47
36#include <asm/netlogic/xlr/iomap.h> 48#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h>
37 50
38void prom_putchar(char c) 51int __cpuinit xlr_wakeup_secondary_cpus(void)
39{ 52{
40 nlm_reg_t *mmio; 53 unsigned int i, boot_cpu;
54
55 /*
56 * In case of RMI boot, hit with NMI to get the cores
57 * from bootloader to linux code.
58 */
59 boot_cpu = hard_smp_processor_id();
60 nlm_set_nmi_handler(nlm_rmiboot_preboot);
61 for (i = 0; i < NR_CPUS; i++) {
62 if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
63 continue;
64 nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
65 }
41 66
42 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 67 return 0;
43 while (netlogic_read_reg(mmio, 0x5) == 0)
44 ;
45 netlogic_write_reg(mmio, 0x0, c);
46} 68}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 00:26:33 -0500