diff options
Diffstat (limited to 'arch/mips/netlogic/common/irq.c')
-rw-r--r-- | arch/mips/netlogic/common/irq.c | 43 |
1 files changed, 15 insertions, 28 deletions
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c index 00dcc7a2bc5a..9f84c60bf535 100644 --- a/arch/mips/netlogic/common/irq.c +++ b/arch/mips/netlogic/common/irq.c | |||
@@ -69,7 +69,7 @@ | |||
69 | #else | 69 | #else |
70 | #define SMP_IRQ_MASK 0 | 70 | #define SMP_IRQ_MASK 0 |
71 | #endif | 71 | #endif |
72 | #define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \ | 72 | #define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \ |
73 | (1ull << IRQ_FMN)) | 73 | (1ull << IRQ_FMN)) |
74 | 74 | ||
75 | struct nlm_pic_irq { | 75 | struct nlm_pic_irq { |
@@ -105,21 +105,23 @@ static void xlp_pic_disable(struct irq_data *d) | |||
105 | static void xlp_pic_mask_ack(struct irq_data *d) | 105 | static void xlp_pic_mask_ack(struct irq_data *d) |
106 | { | 106 | { |
107 | struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); | 107 | struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); |
108 | uint64_t mask = 1ull << pd->picirq; | ||
109 | 108 | ||
110 | write_c0_eirr(mask); /* ack by writing EIRR */ | 109 | clear_c0_eimr(pd->picirq); |
110 | ack_c0_eirr(pd->picirq); | ||
111 | } | 111 | } |
112 | 112 | ||
113 | static void xlp_pic_unmask(struct irq_data *d) | 113 | static void xlp_pic_unmask(struct irq_data *d) |
114 | { | 114 | { |
115 | struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); | 115 | struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); |
116 | 116 | ||
117 | if (!pd) | 117 | BUG_ON(!pd); |
118 | return; | ||
119 | 118 | ||
120 | if (pd->extra_ack) | 119 | if (pd->extra_ack) |
121 | pd->extra_ack(d); | 120 | pd->extra_ack(d); |
122 | 121 | ||
122 | /* re-enable the intr on this cpu */ | ||
123 | set_c0_eimr(pd->picirq); | ||
124 | |||
123 | /* Ack is a single write, no need to lock */ | 125 | /* Ack is a single write, no need to lock */ |
124 | nlm_pic_ack(pd->node->picbase, pd->irt); | 126 | nlm_pic_ack(pd->node->picbase, pd->irt); |
125 | } | 127 | } |
@@ -134,32 +136,17 @@ static struct irq_chip xlp_pic = { | |||
134 | 136 | ||
135 | static void cpuintr_disable(struct irq_data *d) | 137 | static void cpuintr_disable(struct irq_data *d) |
136 | { | 138 | { |
137 | uint64_t eimr; | 139 | clear_c0_eimr(d->irq); |
138 | uint64_t mask = 1ull << d->irq; | ||
139 | |||
140 | eimr = read_c0_eimr(); | ||
141 | write_c0_eimr(eimr & ~mask); | ||
142 | } | 140 | } |
143 | 141 | ||
144 | static void cpuintr_enable(struct irq_data *d) | 142 | static void cpuintr_enable(struct irq_data *d) |
145 | { | 143 | { |
146 | uint64_t eimr; | 144 | set_c0_eimr(d->irq); |
147 | uint64_t mask = 1ull << d->irq; | ||
148 | |||
149 | eimr = read_c0_eimr(); | ||
150 | write_c0_eimr(eimr | mask); | ||
151 | } | 145 | } |
152 | 146 | ||
153 | static void cpuintr_ack(struct irq_data *d) | 147 | static void cpuintr_ack(struct irq_data *d) |
154 | { | 148 | { |
155 | uint64_t mask = 1ull << d->irq; | 149 | ack_c0_eirr(d->irq); |
156 | |||
157 | write_c0_eirr(mask); | ||
158 | } | ||
159 | |||
160 | static void cpuintr_nop(struct irq_data *d) | ||
161 | { | ||
162 | WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq); | ||
163 | } | 150 | } |
164 | 151 | ||
165 | /* | 152 | /* |
@@ -170,9 +157,9 @@ struct irq_chip nlm_cpu_intr = { | |||
170 | .name = "XLP-CPU-INTR", | 157 | .name = "XLP-CPU-INTR", |
171 | .irq_enable = cpuintr_enable, | 158 | .irq_enable = cpuintr_enable, |
172 | .irq_disable = cpuintr_disable, | 159 | .irq_disable = cpuintr_disable, |
173 | .irq_mask = cpuintr_nop, | 160 | .irq_mask = cpuintr_disable, |
174 | .irq_ack = cpuintr_nop, | 161 | .irq_ack = cpuintr_ack, |
175 | .irq_eoi = cpuintr_ack, | 162 | .irq_eoi = cpuintr_enable, |
176 | }; | 163 | }; |
177 | 164 | ||
178 | static void __init nlm_init_percpu_irqs(void) | 165 | static void __init nlm_init_percpu_irqs(void) |
@@ -230,7 +217,7 @@ static void nlm_init_node_irqs(int node) | |||
230 | nlm_setup_pic_irq(node, i, i, irt); | 217 | nlm_setup_pic_irq(node, i, i, irt); |
231 | /* set interrupts to first cpu in node */ | 218 | /* set interrupts to first cpu in node */ |
232 | nlm_pic_init_irt(nodep->picbase, irt, i, | 219 | nlm_pic_init_irt(nodep->picbase, irt, i, |
233 | node * NLM_CPUS_PER_NODE); | 220 | node * NLM_CPUS_PER_NODE, 0); |
234 | irqmask |= (1ull << i); | 221 | irqmask |= (1ull << i); |
235 | } | 222 | } |
236 | nodep->irqmask = irqmask; | 223 | nodep->irqmask = irqmask; |
@@ -265,7 +252,7 @@ asmlinkage void plat_irq_dispatch(void) | |||
265 | int i, node; | 252 | int i, node; |
266 | 253 | ||
267 | node = nlm_nodeid(); | 254 | node = nlm_nodeid(); |
268 | eirr = read_c0_eirr() & read_c0_eimr(); | 255 | eirr = read_c0_eirr_and_eimr(); |
269 | 256 | ||
270 | i = __ilog2_u64(eirr); | 257 | i = __ilog2_u64(eirr); |
271 | if (i == -1) | 258 | if (i == -1) |