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-rw-r--r--arch/mips/mti-malta/malta-init.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index eebb2d1538c6..4f9e44d358b7 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -244,10 +244,23 @@ mips_pci_controller:
244 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 244 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
245 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 245 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
246#endif 246#endif
247#ifndef CONFIG_EVA
247 /* Fix up target memory mapping. */ 248 /* Fix up target memory mapping. */
248 MSC_READ(MSC01_PCI_BAR0, mask); 249 MSC_READ(MSC01_PCI_BAR0, mask);
249 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); 250 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
251#else
252 /*
253 * Setup the Malta max (2GB) memory for PCI DMA in host bridge
254 * in transparent addressing mode, starting from 0x80000000.
255 */
256 mask = PHYS_OFFSET | (1<<3);
257 MSC_WRITE(MSC01_PCI_BAR0, mask);
250 258
259 mask = PHYS_OFFSET;
260 MSC_WRITE(MSC01_PCI_HEAD4, mask);
261 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
262 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
263#endif
251 /* Don't handle target retries indefinitely. */ 264 /* Don't handle target retries indefinitely. */
252 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 265 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
253 MSC01_PCI_CFG_MAXRTRY_MSK) 266 MSC01_PCI_CFG_MAXRTRY_MSK)