3 files changed, 60 insertions, 46 deletions

diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index 475038a141a6..27c807b67fea 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -30,6 +30,7 @@
 #include <asm/cacheflush.h>
 #include <asm/traps.h>
 
+#include <asm/gcmpregs.h>
 #include <asm/mips-boards/prom.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/bonito64.h>
@@ -192,6 +193,8 @@ extern struct plat_smp_ops msmtc_smp_ops;
 
 void __init prom_init(void)
 {
+        int result;
+
         prom_argc = fw_arg0;
         _prom_argv = (int *) fw_arg1;
         _prom_envp = (int *) fw_arg2;
@@ -358,12 +361,21 @@ void __init prom_init(void)
 #ifdef CONFIG_SERIAL_8250_CONSOLE
         console_config();
 #endif
+        /* Early detection of CMP support */
+        result = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
+
 #ifdef CONFIG_MIPS_CMP
-        register_smp_ops(&cmp_smp_ops);
+        if (result)
+                register_smp_ops(&cmp_smp_ops);
 #endif
 #ifdef CONFIG_MIPS_MT_SMP
+#ifdef CONFIG_MIPS_CMP
+        if (!result)
+                register_smp_ops(&vsmp_smp_ops);
+#else
         register_smp_ops(&vsmp_smp_ops);
 #endif
+#endif
 #ifdef CONFIG_MIPS_MT_SMTC
         register_smp_ops(&msmtc_smp_ops);
 #endif
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index b4eaf137e4a7..a8756f82c31b 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -331,6 +331,21 @@ static struct irqaction irq_call = {
         .flags          = IRQF_DISABLED|IRQF_PERCPU,
         .name           = "IPI_call"
 };
+
+static int gic_resched_int_base;
+static int gic_call_int_base;
+#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
+#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
+
+unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
+{
+        return GIC_CALL_INT(cpu);
+}
+
+unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
+{
+        return GIC_RESCHED_INT(cpu);
+}
 #endif /* CONFIG_MIPS_MT_SMP */
 
 static struct irqaction i8259irq = {
@@ -370,7 +385,7 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
  * Interrupts and CPUs/Core Interrupts. The nature of the External
  * Interrupts is also defined here - polarity/trigger.
  */
-static struct gic_intr_map gic_intr_map[] = {
+static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
         { GIC_EXT_INTR(0),      X,      X,              X,              X,              0 },
         { GIC_EXT_INTR(1),      X,      X,              X,              X,              0 },
         { GIC_EXT_INTR(2),      X,      X,              X,              X,              0 },
@@ -387,21 +402,14 @@ static struct gic_intr_map gic_intr_map[] = {
         { GIC_EXT_INTR(13),     0,      GIC_MAP_TO_NMI_MSK,     GIC_POL_POS, GIC_TRIG_LEVEL,    0 },
         { GIC_EXT_INTR(14),     0,      GIC_MAP_TO_NMI_MSK,     GIC_POL_POS, GIC_TRIG_LEVEL,    0 },
         { GIC_EXT_INTR(15),     X,      X,              X,              X,              0 },
-        { GIC_EXT_INTR(16),     0,      GIC_CPU_INT1,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
-        { GIC_EXT_INTR(17),     0,      GIC_CPU_INT2,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
-        { GIC_EXT_INTR(18),     1,      GIC_CPU_INT1,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
-        { GIC_EXT_INTR(19),     1,      GIC_CPU_INT2,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
-        { GIC_EXT_INTR(20),     2,      GIC_CPU_INT1,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
-        { GIC_EXT_INTR(21),     2,      GIC_CPU_INT2,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
-        { GIC_EXT_INTR(22),     3,      GIC_CPU_INT1,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
-        { GIC_EXT_INTR(23),     3,      GIC_CPU_INT2,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+/* This is the end of the general interrupts now we do IPI ones */
 };
 #endif
 
 /*
  * GCMP needs to be detected before any SMP initialisation
  */
-static int __init gcmp_probe(unsigned long addr, unsigned long size)
+int __init gcmp_probe(unsigned long addr, unsigned long size)
 {
         if (gcmp_present >= 0)
                 return gcmp_present;
@@ -416,28 +424,36 @@ static int __init gcmp_probe(unsigned long addr, unsigned long size)
 }
 
 #if defined(CONFIG_MIPS_MT_SMP)
+static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
+{
+        int intr = baseintr + cpu;
+        gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
+        gic_intr_map[intr].cpunum = cpu;
+        gic_intr_map[intr].pin = cpupin;
+        gic_intr_map[intr].polarity = GIC_POL_POS;
+        gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
+        gic_intr_map[intr].ipiflag = 1;
+        ipi_map[cpu] |= (1 << (cpupin + 2));
+}
+
 static void __init fill_ipi_map(void)
 {
-        int i;
+        int cpu;
 
-        for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
-                if (gic_intr_map[i].ipiflag && (gic_intr_map[i].cpunum != X))
-                        ipi_map[gic_intr_map[i].cpunum] |=
-                                (1 << (gic_intr_map[i].pin + 2));
+        for (cpu = 0; cpu < NR_CPUS; cpu++) {
+                fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
+                fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
         }
 }
 #endif
 
 void __init arch_init_irq(void)
 {
-        int gic_present, gcmp_present;
-
         init_i8259_irqs();
 
         if (!cpu_has_veic)
                 mips_cpu_irq_init();
 
-        gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
         if (gcmp_present)  {
                 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
                 gic_present = 1;
@@ -514,24 +530,10 @@ void __init arch_init_irq(void)
         if (gic_present) {
                 /* FIXME */
                 int i;
-                struct {
-                        unsigned int resched;
-                        unsigned int call;
-                } ipiirq[] = {
-                        {
-                                .resched = GIC_IPI_EXT_INTR_RESCHED_VPE0,
-                                .call =  GIC_IPI_EXT_INTR_CALLFNC_VPE0},
-                        {
-                                .resched = GIC_IPI_EXT_INTR_RESCHED_VPE1,
-                                .call =  GIC_IPI_EXT_INTR_CALLFNC_VPE1
-                        }, {
-                                .resched = GIC_IPI_EXT_INTR_RESCHED_VPE2,
-                                .call =  GIC_IPI_EXT_INTR_CALLFNC_VPE2
-                        }, {
-                                .resched = GIC_IPI_EXT_INTR_RESCHED_VPE3,
-                                .call =  GIC_IPI_EXT_INTR_CALLFNC_VPE3
-                        }
-                };
+
+                gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
+                gic_resched_int_base = gic_call_int_base - NR_CPUS;
+
                 fill_ipi_map();
                 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
                 if (!gcmp_present) {
@@ -553,12 +555,15 @@ void __init arch_init_irq(void)
                 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
                 write_c0_status(0x1100dc00);
                 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
-                for (i = 0; i < ARRAY_SIZE(ipiirq); i++) {
-                        setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched);
-                        setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call);
-
-                        set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, handle_percpu_irq);
-                        set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].call, handle_percpu_irq);
+                for (i = 0; i < NR_CPUS; i++) {
+                        setup_irq(MIPS_GIC_IRQ_BASE +
+                                        GIC_RESCHED_INT(i), &irq_resched);
+                        setup_irq(MIPS_GIC_IRQ_BASE +
+                                        GIC_CALL_INT(i), &irq_call);
+                        set_irq_handler(MIPS_GIC_IRQ_BASE +
+                                        GIC_RESCHED_INT(i), handle_percpu_irq);
+                        set_irq_handler(MIPS_GIC_IRQ_BASE +
+                                        GIC_CALL_INT(i), handle_percpu_irq);
                 }
         } else {
                 /* set up ipi interrupts */
diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c
index 42dee4da37ba..f48d60e84290 100644
--- a/arch/mips/mti-malta/malta-reset.c
+++ b/arch/mips/mti-malta/malta-reset.c
@@ -28,9 +28,6 @@
 #include <asm/reboot.h>
 #include <asm/mips-boards/generic.h>
 
-static void mips_machine_restart(char *command);
-static void mips_machine_halt(void);
-
 static void mips_machine_restart(char *command)
 {
         unsigned int __iomem *softres_reg =