diff options
Diffstat (limited to 'arch/mips/mti-malta/malta-pci.c')
-rw-r--r-- | arch/mips/mti-malta/malta-pci.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index b9743190609a..2fbfa1a8c3a9 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c | |||
@@ -27,7 +27,7 @@ | |||
27 | #include <linux/init.h> | 27 | #include <linux/init.h> |
28 | 28 | ||
29 | #include <asm/gt64120.h> | 29 | #include <asm/gt64120.h> |
30 | 30 | #include <asm/gcmpregs.h> | |
31 | #include <asm/mips-boards/generic.h> | 31 | #include <asm/mips-boards/generic.h> |
32 | #include <asm/mips-boards/bonito64.h> | 32 | #include <asm/mips-boards/bonito64.h> |
33 | #include <asm/mips-boards/msc01_pci.h> | 33 | #include <asm/mips-boards/msc01_pci.h> |
@@ -201,7 +201,11 @@ void __init mips_pcibios_init(void) | |||
201 | msc_mem_resource.start = start & mask; | 201 | msc_mem_resource.start = start & mask; |
202 | msc_mem_resource.end = (start & mask) | ~mask; | 202 | msc_mem_resource.end = (start & mask) | ~mask; |
203 | msc_controller.mem_offset = (start & mask) - (map & mask); | 203 | msc_controller.mem_offset = (start & mask) - (map & mask); |
204 | 204 | #ifdef CONFIG_MIPS_CMP | |
205 | if (gcmp_niocu()) | ||
206 | gcmp_setregion(0, start, mask, | ||
207 | GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); | ||
208 | #endif | ||
205 | MSC_READ(MSC01_PCI_SC2PIOBASL, start); | 209 | MSC_READ(MSC01_PCI_SC2PIOBASL, start); |
206 | MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); | 210 | MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); |
207 | MSC_READ(MSC01_PCI_SC2PIOMAPL, map); | 211 | MSC_READ(MSC01_PCI_SC2PIOMAPL, map); |
@@ -209,7 +213,11 @@ void __init mips_pcibios_init(void) | |||
209 | msc_io_resource.end = (map & mask) | ~mask; | 213 | msc_io_resource.end = (map & mask) | ~mask; |
210 | msc_controller.io_offset = 0; | 214 | msc_controller.io_offset = 0; |
211 | ioport_resource.end = ~mask; | 215 | ioport_resource.end = ~mask; |
212 | 216 | #ifdef CONFIG_MIPS_CMP | |
217 | if (gcmp_niocu()) | ||
218 | gcmp_setregion(1, start, mask, | ||
219 | GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); | ||
220 | #endif | ||
213 | /* If ranges overlap I/O takes precedence. */ | 221 | /* If ranges overlap I/O takes precedence. */ |
214 | start = start & mask; | 222 | start = start & mask; |
215 | end = start | ~mask; | 223 | end = start | ~mask; |
@@ -241,3 +249,16 @@ void __init mips_pcibios_init(void) | |||
241 | 249 | ||
242 | register_pci_controller(controller); | 250 | register_pci_controller(controller); |
243 | } | 251 | } |
252 | |||
253 | /* Enable PCI 2.1 compatibility in PIIX4 */ | ||
254 | static void __init quirk_dlcsetup(struct pci_dev *dev) | ||
255 | { | ||
256 | u8 odlc, ndlc; | ||
257 | (void) pci_read_config_byte(dev, 0x82, &odlc); | ||
258 | /* Enable passive releases and delayed transaction */ | ||
259 | ndlc = odlc | 7; | ||
260 | (void) pci_write_config_byte(dev, 0x82, ndlc); | ||
261 | } | ||
262 | |||
263 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, | ||
264 | quirk_dlcsetup); | ||