diff options
Diffstat (limited to 'arch/mips/momentum')
-rw-r--r-- | arch/mips/momentum/jaguar_atx/Makefile | 2 | ||||
-rw-r--r-- | arch/mips/momentum/jaguar_atx/int-handler.S | 128 | ||||
-rw-r--r-- | arch/mips/momentum/jaguar_atx/irq.c | 35 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_3/Makefile | 2 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_3/int-handler.S | 139 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_3/irq.c | 38 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_c/Makefile | 2 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_c/int-handler.S | 103 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_c/irq.c | 30 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/Makefile | 2 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/int-handler.S | 131 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/irq.c | 38 |
12 files changed, 130 insertions, 520 deletions
diff --git a/arch/mips/momentum/jaguar_atx/Makefile b/arch/mips/momentum/jaguar_atx/Makefile index 20bbd3ea44a8..67372f3f9654 100644 --- a/arch/mips/momentum/jaguar_atx/Makefile +++ b/arch/mips/momentum/jaguar_atx/Makefile | |||
@@ -6,7 +6,7 @@ | |||
6 | # unless it's something special (ie not a .c file). | 6 | # unless it's something special (ie not a .c file). |
7 | # | 7 | # |
8 | 8 | ||
9 | obj-y += int-handler.o irq.o prom.o reset.o setup.o | 9 | obj-y += irq.o prom.o reset.o setup.o |
10 | 10 | ||
11 | obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o | 11 | obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o |
12 | obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o | 12 | obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o |
diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S deleted file mode 100644 index 55bc789733f2..000000000000 --- a/arch/mips/momentum/jaguar_atx/int-handler.S +++ /dev/null | |||
@@ -1,128 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2002 Momentum Computer Inc. | ||
3 | * Author: Matthew Dharm <mdharm@momenco.com> | ||
4 | * | ||
5 | * Based on work: | ||
6 | * Copyright 2001 MontaVista Software Inc. | ||
7 | * Author: jsun@mvista.com or jsun@junsun.net | ||
8 | * | ||
9 | * First-level interrupt dispatcher for Jaguar-ATX board. | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify it | ||
12 | * under the terms of the GNU General Public License as published by the | ||
13 | * Free Software Foundation; either version 2 of the License, or (at your | ||
14 | * option) any later version. | ||
15 | */ | ||
16 | #include <asm/asm.h> | ||
17 | #include <asm/mipsregs.h> | ||
18 | #include <asm/addrspace.h> | ||
19 | #include <asm/regdef.h> | ||
20 | #include <asm/stackframe.h> | ||
21 | |||
22 | /* | ||
23 | * First level interrupt dispatcher for Ocelot-CS board | ||
24 | */ | ||
25 | .align 5 | ||
26 | NESTED(jaguar_handle_int, PT_SIZE, sp) | ||
27 | SAVE_ALL | ||
28 | CLI | ||
29 | .set at | ||
30 | mfc0 t0, CP0_CAUSE | ||
31 | mfc0 t2, CP0_STATUS | ||
32 | |||
33 | and t0, t2 | ||
34 | |||
35 | andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ | ||
36 | bnez t1, ll_sw0_irq | ||
37 | andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ | ||
38 | bnez t1, ll_sw1_irq | ||
39 | andi t1, t0, STATUSF_IP2 /* int0 hardware line */ | ||
40 | bnez t1, ll_pcixa_irq | ||
41 | andi t1, t0, STATUSF_IP3 /* int1 hardware line */ | ||
42 | bnez t1, ll_pcixb_irq | ||
43 | andi t1, t0, STATUSF_IP4 /* int2 hardware line */ | ||
44 | bnez t1, ll_pcia_irq | ||
45 | andi t1, t0, STATUSF_IP5 /* int3 hardware line */ | ||
46 | bnez t1, ll_pcib_irq | ||
47 | andi t1, t0, STATUSF_IP6 /* int4 hardware line */ | ||
48 | bnez t1, ll_uart_irq | ||
49 | andi t1, t0, STATUSF_IP7 /* cpu timer */ | ||
50 | bnez t1, ll_cputimer_irq | ||
51 | |||
52 | nop | ||
53 | nop | ||
54 | |||
55 | /* now look at extended interrupts */ | ||
56 | mfc0 t0, CP0_CAUSE | ||
57 | cfc0 t1, CP0_S1_INTCONTROL | ||
58 | |||
59 | /* shift the mask 8 bits left to line up the bits */ | ||
60 | sll t2, t1, 8 | ||
61 | |||
62 | and t0, t2 | ||
63 | srl t0, t0, 16 | ||
64 | |||
65 | andi t1, t0, STATUSF_IP8 /* int6 hardware line */ | ||
66 | bnez t1, ll_mv64340_decode_irq | ||
67 | |||
68 | nop | ||
69 | nop | ||
70 | |||
71 | .set reorder | ||
72 | |||
73 | /* wrong alarm or masked ... */ | ||
74 | j spurious_interrupt | ||
75 | nop | ||
76 | END(jaguar_handle_int) | ||
77 | |||
78 | .align 5 | ||
79 | ll_sw0_irq: | ||
80 | li a0, 0 | ||
81 | move a1, sp | ||
82 | jal do_IRQ | ||
83 | j ret_from_irq | ||
84 | ll_sw1_irq: | ||
85 | li a0, 1 | ||
86 | move a1, sp | ||
87 | jal do_IRQ | ||
88 | j ret_from_irq | ||
89 | ll_pcixa_irq: | ||
90 | li a0, 2 | ||
91 | move a1, sp | ||
92 | jal do_IRQ | ||
93 | j ret_from_irq | ||
94 | |||
95 | ll_pcixb_irq: | ||
96 | li a0, 3 | ||
97 | move a1, sp | ||
98 | jal do_IRQ | ||
99 | j ret_from_irq | ||
100 | |||
101 | ll_pcia_irq: | ||
102 | li a0, 4 | ||
103 | move a1, sp | ||
104 | jal do_IRQ | ||
105 | j ret_from_irq | ||
106 | |||
107 | ll_pcib_irq: | ||
108 | li a0, 5 | ||
109 | move a1, sp | ||
110 | jal do_IRQ | ||
111 | j ret_from_irq | ||
112 | |||
113 | ll_uart_irq: | ||
114 | li a0, 6 | ||
115 | move a1, sp | ||
116 | jal do_IRQ | ||
117 | j ret_from_irq | ||
118 | |||
119 | ll_cputimer_irq: | ||
120 | li a0, 7 | ||
121 | move a1, sp | ||
122 | jal ll_timer_interrupt | ||
123 | j ret_from_irq | ||
124 | |||
125 | ll_mv64340_decode_irq: | ||
126 | move a0, sp | ||
127 | jal ll_mv64340_irq | ||
128 | j ret_from_irq | ||
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c index 15588f91ace2..ec4032b38f19 100644 --- a/arch/mips/momentum/jaguar_atx/irq.c +++ b/arch/mips/momentum/jaguar_atx/irq.c | |||
@@ -10,7 +10,7 @@ | |||
10 | * Copyright 2001 MontaVista Software Inc. | 10 | * Copyright 2001 MontaVista Software Inc. |
11 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | 11 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net |
12 | * | 12 | * |
13 | * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) | 13 | * Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org) |
14 | * | 14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | 15 | * This program is free software; you can redistribute it and/or modify it |
16 | * under the terms of the GNU General Public License as published by the | 16 | * under the terms of the GNU General Public License as published by the |
@@ -38,8 +38,37 @@ | |||
38 | #include <linux/types.h> | 38 | #include <linux/types.h> |
39 | #include <asm/irq_cpu.h> | 39 | #include <asm/irq_cpu.h> |
40 | #include <asm/mipsregs.h> | 40 | #include <asm/mipsregs.h> |
41 | #include <asm/time.h> | ||
41 | 42 | ||
42 | extern asmlinkage void jaguar_handle_int(void); | 43 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) |
44 | { | ||
45 | unsigned int pending = read_c0_cause() & read_c0_status(); | ||
46 | |||
47 | if (pending & STATUSF_IP0) | ||
48 | do_IRQ(0, regs); | ||
49 | else if (pending & STATUSF_IP1) | ||
50 | do_IRQ(1, regs); | ||
51 | else if (pending & STATUSF_IP2) | ||
52 | do_IRQ(2, regs); | ||
53 | else if (pending & STATUSF_IP3) | ||
54 | do_IRQ(3, regs); | ||
55 | else if (pending & STATUSF_IP4) | ||
56 | do_IRQ(4, regs); | ||
57 | else if (pending & STATUSF_IP5) | ||
58 | do_IRQ(5, regs); | ||
59 | else if (pending & STATUSF_IP6) | ||
60 | do_IRQ(6, regs); | ||
61 | else if (pending & STATUSF_IP7) | ||
62 | ll_timer_interrupt(7, regs); | ||
63 | else { | ||
64 | /* | ||
65 | * Now look at the extended interrupts | ||
66 | */ | ||
67 | pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; | ||
68 | if (pending & STATUSF_IP8) | ||
69 | ll_mv64340_irq(regs); | ||
70 | } | ||
71 | } | ||
43 | 72 | ||
44 | static struct irqaction cascade_mv64340 = { | 73 | static struct irqaction cascade_mv64340 = { |
45 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL | 74 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL |
@@ -53,8 +82,6 @@ void __init arch_init_irq(void) | |||
53 | */ | 82 | */ |
54 | clear_c0_status(ST0_IM); | 83 | clear_c0_status(ST0_IM); |
55 | 84 | ||
56 | /* Sets the first-level interrupt dispatcher. */ | ||
57 | set_except_vector(0, jaguar_handle_int); | ||
58 | mips_cpu_irq_init(0); | 85 | mips_cpu_irq_init(0); |
59 | rm7k_cpu_irq_init(8); | 86 | rm7k_cpu_irq_init(8); |
60 | 87 | ||
diff --git a/arch/mips/momentum/ocelot_3/Makefile b/arch/mips/momentum/ocelot_3/Makefile index aab8fd89f830..8bcea64dd27b 100644 --- a/arch/mips/momentum/ocelot_3/Makefile +++ b/arch/mips/momentum/ocelot_3/Makefile | |||
@@ -5,4 +5,4 @@ | |||
5 | # removes any old dependencies. DON'T put your own dependencies here | 5 | # removes any old dependencies. DON'T put your own dependencies here |
6 | # unless it's something special (ie not a .c file). | 6 | # unless it's something special (ie not a .c file). |
7 | # | 7 | # |
8 | obj-y += int-handler.o irq.o prom.o reset.o setup.o | 8 | obj-y += irq.o prom.o reset.o setup.o |
diff --git a/arch/mips/momentum/ocelot_3/int-handler.S b/arch/mips/momentum/ocelot_3/int-handler.S deleted file mode 100644 index b1207262984a..000000000000 --- a/arch/mips/momentum/ocelot_3/int-handler.S +++ /dev/null | |||
@@ -1,139 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2002 Momentum Computer Inc. | ||
3 | * Author: Matthew Dharm <mdharm@momenco.com> | ||
4 | * | ||
5 | * Copyright 2001 MontaVista Software Inc. | ||
6 | * Author: jsun@mvista.com or jsun@junsun.net | ||
7 | * | ||
8 | * Copyright 2004 PMC-Sierra | ||
9 | * Author: Manish Lachwani (lachwani@pmc-sierra.com) | ||
10 | * | ||
11 | * Copyright (C) 2004 MontaVista Software Inc. | ||
12 | * Author: Manish Lachwani, mlachwani@mvista.com | ||
13 | * | ||
14 | * First-level interrupt dispatcher for Ocelot-3 board. | ||
15 | * | ||
16 | * This program is free software; you can redistribute it and/or modify it | ||
17 | * under the terms of the GNU General Public License as published by the | ||
18 | * Free Software Foundation; either version 2 of the License, or (at your | ||
19 | * option) any later version. | ||
20 | */ | ||
21 | #include <asm/asm.h> | ||
22 | #include <asm/mipsregs.h> | ||
23 | #include <asm/addrspace.h> | ||
24 | #include <asm/regdef.h> | ||
25 | #include <asm/stackframe.h> | ||
26 | |||
27 | /* | ||
28 | * First level interrupt dispatcher for Ocelot-3 board | ||
29 | */ | ||
30 | .align 5 | ||
31 | NESTED(ocelot3_handle_int, PT_SIZE, sp) | ||
32 | SAVE_ALL | ||
33 | CLI | ||
34 | .set at | ||
35 | |||
36 | mfc0 t0, CP0_CAUSE | ||
37 | mfc0 t2, CP0_STATUS | ||
38 | |||
39 | and t0, t2 | ||
40 | |||
41 | andi t1, t0, STATUSF_IP0 /* sw0 software interrupt (IRQ0) */ | ||
42 | bnez t1, ll_sw0_irq | ||
43 | |||
44 | andi t1, t0, STATUSF_IP1 /* sw1 software interrupt (IRQ1) */ | ||
45 | bnez t1, ll_sw1_irq | ||
46 | |||
47 | andi t1, t0, STATUSF_IP2 /* int0 hardware line (IRQ2) */ | ||
48 | bnez t1, ll_pci0slot1_irq | ||
49 | |||
50 | andi t1, t0, STATUSF_IP3 /* int1 hardware line (IRQ3) */ | ||
51 | bnez t1, ll_pci0slot2_irq | ||
52 | |||
53 | andi t1, t0, STATUSF_IP4 /* int2 hardware line (IRQ4) */ | ||
54 | bnez t1, ll_pci1slot1_irq | ||
55 | |||
56 | andi t1, t0, STATUSF_IP5 /* int3 hardware line (IRQ5) */ | ||
57 | bnez t1, ll_pci1slot2_irq | ||
58 | |||
59 | andi t1, t0, STATUSF_IP6 /* int4 hardware line (IRQ6) */ | ||
60 | bnez t1, ll_uart_irq | ||
61 | |||
62 | andi t1, t0, STATUSF_IP7 /* cpu timer (IRQ7) */ | ||
63 | bnez t1, ll_cputimer_irq | ||
64 | |||
65 | /* now look at extended interrupts */ | ||
66 | mfc0 t0, CP0_CAUSE | ||
67 | cfc0 t1, CP0_S1_INTCONTROL | ||
68 | |||
69 | /* shift the mask 8 bits left to line up the bits */ | ||
70 | sll t2, t1, 8 | ||
71 | |||
72 | and t0, t2 | ||
73 | srl t0, t0, 16 | ||
74 | |||
75 | andi t1, t0, STATUSF_IP8 /* int6 hardware line (IRQ9) */ | ||
76 | bnez t1, ll_mv64340_decode_irq | ||
77 | |||
78 | .set reorder | ||
79 | |||
80 | /* wrong alarm or masked ... */ | ||
81 | jal spurious_interrupt | ||
82 | nop | ||
83 | j ret_from_irq | ||
84 | nop | ||
85 | END(ocelot3_handle_int) | ||
86 | |||
87 | .align 5 | ||
88 | ll_sw0_irq: | ||
89 | li a0, 0 /* IRQ 1 */ | ||
90 | move a1, sp | ||
91 | jal do_IRQ | ||
92 | j ret_from_irq | ||
93 | ll_sw1_irq: | ||
94 | li a0, 1 /* IRQ 2 */ | ||
95 | move a1, sp | ||
96 | jal do_IRQ | ||
97 | j ret_from_irq | ||
98 | |||
99 | ll_pci0slot1_irq: | ||
100 | li a0, 2 /* IRQ 3 */ | ||
101 | move a1, sp | ||
102 | jal do_IRQ | ||
103 | j ret_from_irq | ||
104 | |||
105 | ll_pci0slot2_irq: | ||
106 | li a0, 3 /* IRQ 4 */ | ||
107 | move a1, sp | ||
108 | jal do_IRQ | ||
109 | j ret_from_irq | ||
110 | |||
111 | ll_pci1slot1_irq: | ||
112 | li a0, 4 /* IRQ 5 */ | ||
113 | move a1, sp | ||
114 | jal do_IRQ | ||
115 | j ret_from_irq | ||
116 | |||
117 | ll_pci1slot2_irq: | ||
118 | li a0, 5 /* IRQ 6 */ | ||
119 | move a1, sp | ||
120 | jal do_IRQ | ||
121 | j ret_from_irq | ||
122 | |||
123 | ll_uart_irq: | ||
124 | li a0, 6 /* IRQ 7 */ | ||
125 | move a1, sp | ||
126 | jal do_IRQ | ||
127 | j ret_from_irq | ||
128 | |||
129 | ll_cputimer_irq: | ||
130 | li a0, 7 /* IRQ 8 */ | ||
131 | move a1, sp | ||
132 | jal do_IRQ | ||
133 | j ret_from_irq | ||
134 | |||
135 | ll_mv64340_decode_irq: | ||
136 | move a0, sp | ||
137 | jal ll_mv64340_irq | ||
138 | j ret_from_irq | ||
139 | |||
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c index 42464dbd4ad2..87c63c340ae3 100644 --- a/arch/mips/momentum/ocelot_3/irq.c +++ b/arch/mips/momentum/ocelot_3/irq.c | |||
@@ -53,8 +53,6 @@ | |||
53 | #include <asm/mipsregs.h> | 53 | #include <asm/mipsregs.h> |
54 | #include <asm/system.h> | 54 | #include <asm/system.h> |
55 | 55 | ||
56 | extern asmlinkage void ocelot3_handle_int(void); | ||
57 | |||
58 | static struct irqaction cascade_mv64340 = { | 56 | static struct irqaction cascade_mv64340 = { |
59 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL | 57 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL |
60 | }; | 58 | }; |
@@ -67,9 +65,6 @@ void __init arch_init_irq(void) | |||
67 | */ | 65 | */ |
68 | clear_c0_status(ST0_IM | ST0_BEV); | 66 | clear_c0_status(ST0_IM | ST0_BEV); |
69 | 67 | ||
70 | /* Sets the first-level interrupt dispatcher. */ | ||
71 | set_except_vector(0, ocelot3_handle_int); | ||
72 | mips_cpu_irq_init(0); | ||
73 | rm7k_cpu_irq_init(8); | 68 | rm7k_cpu_irq_init(8); |
74 | 69 | ||
75 | /* set up the cascading interrupts */ | 70 | /* set up the cascading interrupts */ |
@@ -79,3 +74,36 @@ void __init arch_init_irq(void) | |||
79 | set_c0_status(ST0_IM); /* IE in the status register */ | 74 | set_c0_status(ST0_IM); /* IE in the status register */ |
80 | 75 | ||
81 | } | 76 | } |
77 | |||
78 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) | ||
79 | { | ||
80 | unsigned int pending = read_c0_cause() & read_c0_status(); | ||
81 | |||
82 | if (pending & STATUSF_IP0) | ||
83 | do_IRQ(0, regs); | ||
84 | else if (pending & STATUSF_IP1) | ||
85 | do_IRQ(1, regs); | ||
86 | else if (pending & STATUSF_IP2) | ||
87 | do_IRQ(2, regs); | ||
88 | else if (pending & STATUSF_IP3) | ||
89 | do_IRQ(3, regs); | ||
90 | else if (pending & STATUSF_IP4) | ||
91 | do_IRQ(4, regs); | ||
92 | else if (pending & STATUSF_IP5) | ||
93 | do_IRQ(5, regs); | ||
94 | else if (pending & STATUSF_IP6) | ||
95 | do_IRQ(6, regs); | ||
96 | else if (pending & STATUSF_IP7) | ||
97 | do_IRQ(7, regs); | ||
98 | else { | ||
99 | /* | ||
100 | * Now look at the extended interrupts | ||
101 | */ | ||
102 | pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; | ||
103 | |||
104 | if (pending & STATUSF_IP8) | ||
105 | ll_mv64340_irq(regs); | ||
106 | else | ||
107 | spurious_interrupt(regs); | ||
108 | } | ||
109 | } | ||
diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile index 91240777f978..94802b4db472 100644 --- a/arch/mips/momentum/ocelot_c/Makefile +++ b/arch/mips/momentum/ocelot_c/Makefile | |||
@@ -2,7 +2,7 @@ | |||
2 | # Makefile for Momentum Computer's Ocelot-C and -CS boards. | 2 | # Makefile for Momentum Computer's Ocelot-C and -CS boards. |
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y += cpci-irq.o int-handler.o irq.o prom.o reset.o \ | 5 | obj-y += cpci-irq.o irq.o prom.o reset.o \ |
6 | setup.o uart-irq.o | 6 | setup.o uart-irq.o |
7 | 7 | ||
8 | obj-$(CONFIG_KGDB) += dbg_io.o | 8 | obj-$(CONFIG_KGDB) += dbg_io.o |
diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S deleted file mode 100644 index f77834193c3c..000000000000 --- a/arch/mips/momentum/ocelot_c/int-handler.S +++ /dev/null | |||
@@ -1,103 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2002 Momentum Computer Inc. | ||
3 | * Author: Matthew Dharm <mdharm@momenco.com> | ||
4 | * | ||
5 | * Copyright 2001 MontaVista Software Inc. | ||
6 | * Author: jsun@mvista.com or jsun@junsun.net | ||
7 | * | ||
8 | * First-level interrupt dispatcher for Ocelot-CS board. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | #include <asm/asm.h> | ||
16 | #include <asm/mipsregs.h> | ||
17 | #include <asm/addrspace.h> | ||
18 | #include <asm/regdef.h> | ||
19 | #include <asm/stackframe.h> | ||
20 | #include "ocelot_c_fpga.h" | ||
21 | |||
22 | /* | ||
23 | * First level interrupt dispatcher for Ocelot-CS board | ||
24 | */ | ||
25 | .align 5 | ||
26 | NESTED(ocelot_handle_int, PT_SIZE, sp) | ||
27 | SAVE_ALL | ||
28 | CLI | ||
29 | .set at | ||
30 | mfc0 t0, CP0_CAUSE | ||
31 | mfc0 t2, CP0_STATUS | ||
32 | |||
33 | and t0, t2 | ||
34 | |||
35 | andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ | ||
36 | bnez t1, ll_sw0_irq | ||
37 | andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ | ||
38 | bnez t1, ll_sw1_irq | ||
39 | andi t1, t0, STATUSF_IP2 /* int0 hardware line */ | ||
40 | bnez t1, ll_scsi_irq | ||
41 | andi t1, t0, STATUSF_IP3 /* int1 hardware line */ | ||
42 | bnez t1, ll_uart_decode_irq | ||
43 | andi t1, t0, STATUSF_IP4 /* int2 hardware line */ | ||
44 | bnez t1, ll_pmc_irq | ||
45 | andi t1, t0, STATUSF_IP5 /* int3 hardware line */ | ||
46 | bnez t1, ll_cpci_decode_irq | ||
47 | andi t1, t0, STATUSF_IP6 /* int4 hardware line */ | ||
48 | bnez t1, ll_mv64340_decode_irq | ||
49 | andi t1, t0, STATUSF_IP7 /* cpu timer */ | ||
50 | bnez t1, ll_cputimer_irq | ||
51 | |||
52 | .set reorder | ||
53 | |||
54 | /* wrong alarm or masked ... */ | ||
55 | jal spurious_interrupt | ||
56 | nop | ||
57 | j ret_from_irq | ||
58 | END(ocelot_handle_int) | ||
59 | |||
60 | .align 5 | ||
61 | ll_sw0_irq: | ||
62 | li a0, 0 | ||
63 | move a1, sp | ||
64 | jal do_IRQ | ||
65 | j ret_from_irq | ||
66 | ll_sw1_irq: | ||
67 | li a0, 1 | ||
68 | move a1, sp | ||
69 | jal do_IRQ | ||
70 | j ret_from_irq | ||
71 | ll_scsi_irq: | ||
72 | li a0, 2 | ||
73 | move a1, sp | ||
74 | jal do_IRQ | ||
75 | j ret_from_irq | ||
76 | |||
77 | ll_uart_decode_irq: | ||
78 | move a0, sp | ||
79 | jal ll_uart_irq | ||
80 | j ret_from_irq | ||
81 | |||
82 | ll_pmc_irq: | ||
83 | li a0, 4 | ||
84 | move a1, sp | ||
85 | jal do_IRQ | ||
86 | j ret_from_irq | ||
87 | |||
88 | ll_cpci_decode_irq: | ||
89 | move a0, sp | ||
90 | jal ll_cpci_irq | ||
91 | j ret_from_irq | ||
92 | |||
93 | ll_mv64340_decode_irq: | ||
94 | move a0, sp | ||
95 | jal ll_mv64340_irq | ||
96 | j ret_from_irq | ||
97 | |||
98 | ll_cputimer_irq: | ||
99 | li a0, 7 | ||
100 | move a1, sp | ||
101 | jal do_IRQ | ||
102 | j ret_from_irq | ||
103 | |||
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c index a5764bc20e36..86f61ce59e53 100644 --- a/arch/mips/momentum/ocelot_c/irq.c +++ b/arch/mips/momentum/ocelot_c/irq.c | |||
@@ -48,7 +48,6 @@ | |||
48 | #include <asm/mipsregs.h> | 48 | #include <asm/mipsregs.h> |
49 | #include <asm/system.h> | 49 | #include <asm/system.h> |
50 | 50 | ||
51 | extern asmlinkage void ocelot_handle_int(void); | ||
52 | extern void uart_irq_init(void); | 51 | extern void uart_irq_init(void); |
53 | extern void cpci_irq_init(void); | 52 | extern void cpci_irq_init(void); |
54 | 53 | ||
@@ -60,6 +59,33 @@ static struct irqaction cascade_mv64340 = { | |||
60 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL | 59 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL |
61 | }; | 60 | }; |
62 | 61 | ||
62 | extern void ll_uart_irq(struct pt_regs *regs); | ||
63 | extern void ll_cpci_irq(struct pt_regs *regs); | ||
64 | |||
65 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) | ||
66 | { | ||
67 | unsigned int pending = read_c0_cause() & read_c0_status(); | ||
68 | |||
69 | if (pending & STATUSF_IP0) | ||
70 | do_IRQ(0, regs); | ||
71 | else if (pending & STATUSF_IP1) | ||
72 | do_IRQ(1, regs); | ||
73 | else if (pending & STATUSF_IP2) | ||
74 | do_IRQ(2, regs); | ||
75 | else if (pending & STATUSF_IP3) | ||
76 | ll_uart_irq(regs); | ||
77 | else if (pending & STATUSF_IP4) | ||
78 | do_IRQ(4, regs); | ||
79 | else if (pending & STATUSF_IP5) | ||
80 | ll_cpci_irq(regs); | ||
81 | else if (pending & STATUSF_IP6) | ||
82 | ll_mv64340_irq(regs); | ||
83 | else if (pending & STATUSF_IP7) | ||
84 | do_IRQ(7, regs); | ||
85 | else | ||
86 | spurious_interrupt(regs); | ||
87 | } | ||
88 | |||
63 | void __init arch_init_irq(void) | 89 | void __init arch_init_irq(void) |
64 | { | 90 | { |
65 | /* | 91 | /* |
@@ -68,8 +94,6 @@ void __init arch_init_irq(void) | |||
68 | */ | 94 | */ |
69 | clear_c0_status(ST0_IM); | 95 | clear_c0_status(ST0_IM); |
70 | 96 | ||
71 | /* Sets the first-level interrupt dispatcher. */ | ||
72 | set_except_vector(0, ocelot_handle_int); | ||
73 | mips_cpu_irq_init(0); | 97 | mips_cpu_irq_init(0); |
74 | 98 | ||
75 | /* set up the cascading interrupts */ | 99 | /* set up the cascading interrupts */ |
diff --git a/arch/mips/momentum/ocelot_g/Makefile b/arch/mips/momentum/ocelot_g/Makefile index e5f1cb086973..adb5665d40a9 100644 --- a/arch/mips/momentum/ocelot_g/Makefile +++ b/arch/mips/momentum/ocelot_g/Makefile | |||
@@ -2,7 +2,7 @@ | |||
2 | # Makefile for Momentum Computer's Ocelot-G board. | 2 | # Makefile for Momentum Computer's Ocelot-G board. |
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y += int-handler.o irq.o gt-irq.o prom.o reset.o setup.o | 5 | obj-y += irq.o gt-irq.o prom.o reset.o setup.o |
6 | obj-$(CONFIG_KGDB) += dbg_io.o | 6 | obj-$(CONFIG_KGDB) += dbg_io.o |
7 | 7 | ||
8 | EXTRA_AFLAGS := $(CFLAGS) | 8 | EXTRA_AFLAGS := $(CFLAGS) |
diff --git a/arch/mips/momentum/ocelot_g/int-handler.S b/arch/mips/momentum/ocelot_g/int-handler.S deleted file mode 100644 index 772e8f713176..000000000000 --- a/arch/mips/momentum/ocelot_g/int-handler.S +++ /dev/null | |||
@@ -1,131 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2001 MontaVista Software Inc. | ||
3 | * Author: jsun@mvista.com or jsun@junsun.net | ||
4 | * | ||
5 | * First-level interrupt dispatcher for ocelot board. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the | ||
9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
10 | * option) any later version. | ||
11 | */ | ||
12 | #include <asm/asm.h> | ||
13 | #include <asm/mipsregs.h> | ||
14 | #include <asm/addrspace.h> | ||
15 | #include <asm/regdef.h> | ||
16 | #include <asm/stackframe.h> | ||
17 | |||
18 | /* | ||
19 | * first level interrupt dispatcher for ocelot board - | ||
20 | * We check for the timer first, then check PCI ints A and D. | ||
21 | * Then check for serial IRQ and fall through. | ||
22 | */ | ||
23 | .align 5 | ||
24 | NESTED(ocelot_handle_int, PT_SIZE, sp) | ||
25 | SAVE_ALL | ||
26 | CLI | ||
27 | .set at | ||
28 | mfc0 t0, CP0_CAUSE | ||
29 | mfc0 t2, CP0_STATUS | ||
30 | |||
31 | and t0, t2 | ||
32 | |||
33 | andi t1, t0, STATUSF_IP2 /* int0 hardware line */ | ||
34 | bnez t1, ll_pri_enet_irq | ||
35 | andi t1, t0, STATUSF_IP3 /* int1 hardware line */ | ||
36 | bnez t1, ll_sec_enet_irq | ||
37 | andi t1, t0, STATUSF_IP4 /* int2 hardware line */ | ||
38 | bnez t1, ll_uart_irq | ||
39 | andi t1, t0, STATUSF_IP5 /* int3 hardware line */ | ||
40 | bnez t1, ll_cpci_irq | ||
41 | andi t1, t0, STATUSF_IP6 /* int4 hardware line */ | ||
42 | bnez t1, ll_galileo_p0_irq | ||
43 | andi t1, t0, STATUSF_IP7 /* cpu timer */ | ||
44 | bnez t1, ll_cputimer_irq | ||
45 | |||
46 | /* now look at the extended interrupts */ | ||
47 | mfc0 t0, CP0_CAUSE | ||
48 | cfc0 t1, CP0_S1_INTCONTROL | ||
49 | |||
50 | /* shift the mask 8 bits left to line up the bits */ | ||
51 | sll t2, t1, 8 | ||
52 | |||
53 | and t0, t2 | ||
54 | srl t0, t0, 16 | ||
55 | |||
56 | andi t1, t0, STATUSF_IP8 /* int6 hardware line */ | ||
57 | bnez t1, ll_galileo_p1_irq | ||
58 | andi t1, t0, STATUSF_IP9 /* int7 hardware line */ | ||
59 | bnez t1, ll_pmc_irq | ||
60 | andi t1, t0, STATUSF_IP10 /* int8 hardware line */ | ||
61 | bnez t1, ll_cpci_abcd_irq | ||
62 | andi t1, t0, STATUSF_IP11 /* int9 hardware line */ | ||
63 | bnez t1, ll_testpoint_irq | ||
64 | |||
65 | .set reorder | ||
66 | |||
67 | /* wrong alarm or masked ... */ | ||
68 | j spurious_interrupt | ||
69 | nop | ||
70 | END(ocelot_handle_int) | ||
71 | |||
72 | .align 5 | ||
73 | ll_pri_enet_irq: | ||
74 | li a0, 2 | ||
75 | move a1, sp | ||
76 | jal do_IRQ | ||
77 | j ret_from_irq | ||
78 | |||
79 | ll_sec_enet_irq: | ||
80 | li a0, 3 | ||
81 | move a1, sp | ||
82 | jal do_IRQ | ||
83 | j ret_from_irq | ||
84 | |||
85 | ll_uart_irq: | ||
86 | li a0, 4 | ||
87 | move a1, sp | ||
88 | jal do_IRQ | ||
89 | j ret_from_irq | ||
90 | |||
91 | ll_cpci_irq: | ||
92 | li a0, 5 | ||
93 | move a1, sp | ||
94 | jal do_IRQ | ||
95 | j ret_from_irq | ||
96 | |||
97 | ll_galileo_p0_irq: | ||
98 | li a0, 6 | ||
99 | move a1, sp | ||
100 | jal do_IRQ | ||
101 | j ret_from_irq | ||
102 | |||
103 | ll_cputimer_irq: | ||
104 | li a0, 7 | ||
105 | move a1, sp | ||
106 | jal do_IRQ | ||
107 | j ret_from_irq | ||
108 | |||
109 | ll_galileo_p1_irq: | ||
110 | li a0, 8 | ||
111 | move a1, sp | ||
112 | jal do_IRQ | ||
113 | j ret_from_irq | ||
114 | |||
115 | ll_pmc_irq: | ||
116 | li a0, 9 | ||
117 | move a1, sp | ||
118 | jal do_IRQ | ||
119 | j ret_from_irq | ||
120 | |||
121 | ll_cpci_abcd_irq: | ||
122 | li a0, 10 | ||
123 | move a1, sp | ||
124 | jal do_IRQ | ||
125 | j ret_from_irq | ||
126 | |||
127 | ll_testpoint_irq: | ||
128 | li a0, 11 | ||
129 | move a1, sp | ||
130 | jal do_IRQ | ||
131 | j ret_from_irq | ||
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c index 5eb85b164205..7a4a419804f1 100644 --- a/arch/mips/momentum/ocelot_g/irq.c +++ b/arch/mips/momentum/ocelot_g/irq.c | |||
@@ -48,7 +48,41 @@ | |||
48 | #include <asm/mipsregs.h> | 48 | #include <asm/mipsregs.h> |
49 | #include <asm/system.h> | 49 | #include <asm/system.h> |
50 | 50 | ||
51 | extern asmlinkage void ocelot_handle_int(void); | 51 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) |
52 | { | ||
53 | unsigned int pending = read_c0_cause() & read_c0_status(); | ||
54 | |||
55 | if (pending & STATUSF_IP2) | ||
56 | do_IRQ(2, regs); | ||
57 | else if (pending & STATUSF_IP3) | ||
58 | do_IRQ(3, regs); | ||
59 | else if (pending & STATUSF_IP4) | ||
60 | do_IRQ(4, regs); | ||
61 | else if (pending & STATUSF_IP5) | ||
62 | do_IRQ(5, regs); | ||
63 | else if (pending & STATUSF_IP6) | ||
64 | do_IRQ(6, regs); | ||
65 | else if (pending & STATUSF_IP7) | ||
66 | do_IRQ(7, regs); | ||
67 | else { | ||
68 | /* | ||
69 | * Now look at the extended interrupts | ||
70 | */ | ||
71 | pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; | ||
72 | |||
73 | if (pending & STATUSF_IP8) | ||
74 | do_IRQ(8, regs); | ||
75 | else if (pending & STATUSF_IP9) | ||
76 | do_IRQ(9, regs); | ||
77 | else if (pending & STATUSF_IP10) | ||
78 | do_IRQ(10, regs); | ||
79 | else if (pending & STATUSF_IP11) | ||
80 | do_IRQ(11, regs); | ||
81 | else | ||
82 | spurious_interrupt(regs); | ||
83 | } | ||
84 | } | ||
85 | |||
52 | extern void gt64240_irq_init(void); | 86 | extern void gt64240_irq_init(void); |
53 | 87 | ||
54 | void __init arch_init_irq(void) | 88 | void __init arch_init_irq(void) |
@@ -60,8 +94,6 @@ void __init arch_init_irq(void) | |||
60 | clear_c0_status(ST0_IM); | 94 | clear_c0_status(ST0_IM); |
61 | local_irq_disable(); | 95 | local_irq_disable(); |
62 | 96 | ||
63 | /* Sets the first-level interrupt dispatcher. */ | ||
64 | set_except_vector(0, ocelot_handle_int); | ||
65 | mips_cpu_irq_init(0); | 97 | mips_cpu_irq_init(0); |
66 | rm7k_cpu_irq_init(8); | 98 | rm7k_cpu_irq_init(8); |
67 | 99 | ||