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-rw-r--r--arch/mips/momentum/ocelot_g/gt-irq.c212
1 files changed, 0 insertions, 212 deletions
diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c
deleted file mode 100644
index e5576bd50fa9..000000000000
--- a/arch/mips/momentum/ocelot_g/gt-irq.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 *
3 * Copyright 2002 Momentum Computer
4 * Author: mdharm@momenco.com
5 *
6 * arch/mips/momentum/ocelot_g/gt_irq.c
7 * Interrupt routines for gt64240. Currently it only handles timer irq.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/kernel_stat.h>
19#include <asm/gt64240.h>
20#include <asm/io.h>
21
22unsigned long bus_clock;
23
24/*
25 * These are interrupt handlers for the GT on-chip interrupts. They
26 * all come in to the MIPS on a single interrupt line, and have to
27 * be handled and ack'ed differently than other MIPS interrupts.
28 */
29
30#if 0
31
32struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
33void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
34
35/*
36 * Hooks IRQ handler to the system. When the system is interrupted
37 * the interrupt service routine is called.
38 *
39 * Inputs :
40 * int_cause - The interrupt cause number. In EVB64120 two parameters
41 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
42 * bit_num - Indicates which bit number in the cause register
43 * isr_ptr - Pointer to the interrupt service routine
44 */
45void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
46{
47 irq_handlers[int_cause][bit_num].routine = isr_ptr;
48}
49
50
51/*
52 * Enables the IRQ on Galileo Chip
53 *
54 * Inputs :
55 * int_cause - The interrupt cause number. In EVB64120 two parameters
56 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
57 * bit_num - Indicates which bit number in the cause register
58 *
59 * Outputs :
60 * 1 if successful, 0 if failure
61 */
62int enable_galileo_irq(int int_cause, int bit_num)
63{
64 if (int_cause == INT_CAUSE_MAIN)
65 SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
66 else if (int_cause == INT_CAUSE_HIGH)
67 SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
68 (1 << bit_num));
69 else
70 return 0;
71
72 return 1;
73}
74
75/*
76 * Disables the IRQ on Galileo Chip
77 *
78 * Inputs :
79 * int_cause - The interrupt cause number. In EVB64120 two parameters
80 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
81 * bit_num - Indicates which bit number in the cause register
82 *
83 * Outputs :
84 * 1 if successful, 0 if failure
85 */
86int disable_galileo_irq(int int_cause, int bit_num)
87{
88 if (int_cause == INT_CAUSE_MAIN)
89 RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
90 (1 << bit_num));
91 else if (int_cause == INT_CAUSE_HIGH)
92 RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
93 (1 << bit_num));
94 else
95 return 0;
96 return 1;
97}
98#endif /* 0 */
99
100/*
101 * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
102 *
103 * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
104 * routine can handle, for now.
105 *
106 * In the future, we'll route more interrupts to this pin, and that's why
107 * we keep this particular structure in the function.
108 */
109
110static irqreturn_t gt64240_p0int_irq(int irq, void *dev)
111{
112 uint32_t irq_src, irq_src_mask;
113 int handled;
114
115 /* get the low interrupt cause register */
116 irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER);
117
118 /* get the mask register for this pin */
119 irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW);
120
121 /* mask off only the interrupts we're interested in */
122 irq_src = irq_src & irq_src_mask;
123
124 handled = IRQ_NONE;
125
126 /* Check for timer interrupt */
127 if (irq_src & 0x00000100) {
128 handled = IRQ_HANDLED;
129 irq_src &= ~0x00000100;
130
131 /* Clear any pending cause bits */
132 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
133
134 /* handle the timer call */
135 do_timer(1);
136#ifndef CONFIG_SMP
137 update_process_times(user_mode(get_irq_regs()));
138#endif
139 }
140
141 if (irq_src) {
142 printk(KERN_INFO
143 "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
144 irq_src);
145 }
146
147 return handled;
148}
149
150/*
151 * Initializes timer using galileo's built in timer.
152 */
153
154/*
155 * This will ignore the standard MIPS timer interrupt handler
156 * that is passed in as *irq (=irq0 in ../kernel/time.c).
157 * We will do our own timer interrupt handling.
158 */
159void gt64240_time_init(void)
160{
161 static struct irqaction timer;
162
163 /* Stop the timer -- we'll use timer #0 */
164 MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
165
166 /* Load timer value for 100 Hz */
167 MV_WRITE(TIMER_COUNTER0, bus_clock / 100);
168
169 /*
170 * Create the IRQ structure entry for the timer. Since we're too early
171 * in the boot process to use the "request_irq()" call, we'll hard-code
172 * the values to the correct interrupt line.
173 */
174 timer.handler = &gt64240_p0int_irq;
175 timer.flags = IRQF_SHARED | IRQF_DISABLED;
176 timer.name = "timer";
177 timer.dev_id = NULL;
178 timer.next = NULL;
179 timer.mask = CPU_MASK_NONE;
180 irq_desc[6].action = &timer;
181
182 enable_irq(6);
183
184 /* Clear any pending cause bits */
185 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
186
187 /* Enable the interrupt for timer 0 */
188 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
189
190 /* Enable the timer interrupt for GT-64240 pin P0_INT# */
191 MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
192
193 /* Configure and start the timer */
194 MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
195}
196
197void gt64240_irq_init(void)
198{
199#if 0
200 int i, j;
201
202 /* Reset irq handlers pointers to NULL */
203 for (i = 0; i < MAX_CAUSE_REGS; i++) {
204 for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
205 irq_handlers[i][j].next = NULL;
206 irq_handlers[i][j].sync = 0;
207 irq_handlers[i][j].routine = NULL;
208 irq_handlers[i][j].data = NULL;
209 }
210 }
211#endif /* 0 */
212}
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