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Diffstat (limited to 'arch/mips/momentum/ocelot_3/setup.c')
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
index 370e75d0e75c..c69195234309 100644
--- a/arch/mips/momentum/ocelot_3/setup.c
+++ b/arch/mips/momentum/ocelot_3/setup.c
@@ -329,22 +329,22 @@ void __init plat_setup(void)
329 /* shut down ethernet ports, just to be sure our memory doesn't get 329 /* shut down ethernet ports, just to be sure our memory doesn't get
330 * corrupted by random ethernet traffic. 330 * corrupted by random ethernet traffic.
331 */ 331 */
332 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); 332 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
333 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); 333 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
334 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); 334 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
335 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); 335 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
336 do {} 336 do {}
337 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); 337 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
338 do {} 338 do {}
339 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); 339 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
340 do {} 340 do {}
341 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); 341 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
342 do {} 342 do {}
343 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); 343 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
344 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), 344 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
345 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); 345 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
346 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), 346 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
347 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); 347 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
348 348
349 /* Turn off the Bit-Error LED */ 349 /* Turn off the Bit-Error LED */
350 OCELOT_FPGA_WRITE(0x80, CLR); 350 OCELOT_FPGA_WRITE(0x80, CLR);