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-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c475
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diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
deleted file mode 100644
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1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Jaguar-ATX board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org)
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 */
42#include <linux/bcd.h>
43#include <linux/init.h>
44#include <linux/kernel.h>
45#include <linux/types.h>
46#include <linux/mm.h>
47#include <linux/bootmem.h>
48#include <linux/module.h>
49#include <linux/pci.h>
50#include <linux/swap.h>
51#include <linux/ioport.h>
52#include <linux/pm.h>
53#include <linux/sched.h>
54#include <linux/interrupt.h>
55#include <linux/timex.h>
56#include <linux/vmalloc.h>
57#include <linux/mv643xx.h>
58
59#include <asm/time.h>
60#include <asm/bootinfo.h>
61#include <asm/page.h>
62#include <asm/io.h>
63#include <asm/irq.h>
64#include <asm/processor.h>
65#include <asm/reboot.h>
66#include <asm/tlbflush.h>
67
68#include "jaguar_atx_fpga.h"
69
70extern unsigned long mv64340_sram_base;
71unsigned long cpu_clock;
72
73/* These functions are used for rebooting or halting the machine*/
74extern void momenco_jaguar_restart(char *command);
75extern void momenco_jaguar_halt(void);
76extern void momenco_jaguar_power_off(void);
77
78void momenco_time_init(void);
79
80static char reset_reason;
81
82static inline unsigned long ENTRYLO(unsigned long paddr)
83{
84 return ((paddr & PAGE_MASK) |
85 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
86 _CACHE_UNCACHED)) >> 6;
87}
88
89void __init bus_error_init(void) { /* nothing */ }
90
91/*
92 * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
93 * to be hit on every IRQ anyway - there's absolutely no point in letting it be
94 * a random TLB entry, as it'll just cause needless churning of the TLB. And we
95 * use the other half for the serial port, which is just a PITA otherwise :)
96 *
97 * Device Physical Virtual
98 * MV64340 Internal Regs 0xf4000000 0xf4000000
99 * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
100 * NVRAM (CS1) 0xfc800000 0xfc800000
101 * UARTs (CS2) 0xfd000000 0xfd000000
102 * Internal SRAM 0xfe000000 0xfe000000
103 * M-Systems DOC (CS3) 0xff000000 0xff000000
104 */
105
106static __init void wire_stupidity_into_tlb(void)
107{
108#ifdef CONFIG_32BIT
109 write_c0_wired(0);
110 local_flush_tlb_all();
111
112 /* marvell and extra space */
113 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
114 0xf4000000UL, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
117 0xfc000000UL, PM_16M);
118// /* m-sys and internal SRAM */
119// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
120// 0xfe000000UL, PM_16M);
121
122 marvell_base = 0xf4000000;
123 //mv64340_sram_base = 0xfe000000; /* Currently unused */
124#endif
125}
126
127unsigned long marvell_base = 0xf4000000L;
128unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
129unsigned long uart_base = 0xfd000000L;
130static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
131
132EXPORT_SYMBOL(marvell_base);
133
134static __init int per_cpu_mappings(void)
135{
136 marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
137 ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
138 uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
139 rtc_base = ioremap(0xfc000000UL, 0x8000);
140 // ioremap(0xfe000000, 32 << 20);
141 write_c0_wired(0);
142 local_flush_tlb_all();
143 ja_setup_console();
144
145 return 0;
146}
147arch_initcall(per_cpu_mappings);
148
149unsigned long m48t37y_get_time(void)
150{
151 unsigned int year, month, day, hour, min, sec;
152 unsigned long flags;
153
154 spin_lock_irqsave(&rtc_lock, flags);
155 /* stop the update */
156 rtc_base[0x7ff8] = 0x40;
157
158 year = BCD2BIN(rtc_base[0x7fff]);
159 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
160
161 month = BCD2BIN(rtc_base[0x7ffe]);
162
163 day = BCD2BIN(rtc_base[0x7ffd]);
164
165 hour = BCD2BIN(rtc_base[0x7ffb]);
166 min = BCD2BIN(rtc_base[0x7ffa]);
167 sec = BCD2BIN(rtc_base[0x7ff9]);
168
169 /* start the update */
170 rtc_base[0x7ff8] = 0x00;
171 spin_unlock_irqrestore(&rtc_lock, flags);
172
173 return mktime(year, month, day, hour, min, sec);
174}
175
176int m48t37y_set_time(unsigned long sec)
177{
178 struct rtc_time tm;
179 unsigned long flags;
180
181 /* convert to a more useful format -- note months count from 0 */
182 to_tm(sec, &tm);
183 tm.tm_mon += 1;
184
185 spin_lock_irqsave(&rtc_lock, flags);
186 /* enable writing */
187 rtc_base[0x7ff8] = 0x80;
188
189 /* year */
190 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
191 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
192
193 /* month */
194 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
195
196 /* day */
197 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
198
199 /* hour/min/sec */
200 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
201 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
202 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
203
204 /* day of week -- not really used, but let's keep it up-to-date */
205 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
206
207 /* disable writing */
208 rtc_base[0x7ff8] = 0x00;
209 spin_unlock_irqrestore(&rtc_lock, flags);
210
211 return 0;
212}
213
214void __init plat_timer_setup(struct irqaction *irq)
215{
216 setup_irq(8, irq);
217}
218
219/*
220 * Ugly but the least of all evils. TLB initialization did flush the TLB so
221 * We need to setup mappings again before we can touch the RTC.
222 */
223void momenco_time_init(void)
224{
225 wire_stupidity_into_tlb();
226
227 mips_hpt_frequency = cpu_clock / 2;
228
229 rtc_mips_get_time = m48t37y_get_time;
230 rtc_mips_set_time = m48t37y_set_time;
231}
232
233static struct resource mv_pci_io_mem0_resource = {
234 .name = "MV64340 PCI0 IO MEM",
235 .flags = IORESOURCE_IO
236};
237
238static struct resource mv_pci_mem0_resource = {
239 .name = "MV64340 PCI0 MEM",
240 .flags = IORESOURCE_MEM
241};
242
243static struct mv_pci_controller mv_bus0_controller = {
244 .pcic = {
245 .pci_ops = &mv_pci_ops,
246 .mem_resource = &mv_pci_mem0_resource,
247 .io_resource = &mv_pci_io_mem0_resource,
248 },
249 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
250 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
251};
252
253static uint32_t mv_io_base, mv_io_size;
254
255static void ja_pci0_init(void)
256{
257 uint32_t mem0_base, mem0_size;
258 uint32_t io_base, io_size;
259
260 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
261 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
262 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
263 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
264
265 mv_pci_io_mem0_resource.start = 0;
266 mv_pci_io_mem0_resource.end = io_size - 1;
267 mv_pci_mem0_resource.start = mem0_base;
268 mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
269 mv_bus0_controller.pcic.mem_offset = mem0_base;
270 mv_bus0_controller.pcic.io_offset = 0;
271
272 ioport_resource.end = io_size - 1;
273
274 register_pci_controller(&mv_bus0_controller.pcic);
275
276 mv_io_base = io_base;
277 mv_io_size = io_size;
278}
279
280static struct resource mv_pci_io_mem1_resource = {
281 .name = "MV64340 PCI1 IO MEM",
282 .flags = IORESOURCE_IO
283};
284
285static struct resource mv_pci_mem1_resource = {
286 .name = "MV64340 PCI1 MEM",
287 .flags = IORESOURCE_MEM
288};
289
290static struct mv_pci_controller mv_bus1_controller = {
291 .pcic = {
292 .pci_ops = &mv_pci_ops,
293 .mem_resource = &mv_pci_mem1_resource,
294 .io_resource = &mv_pci_io_mem1_resource,
295 },
296 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
297 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
298};
299
300static __init void ja_pci1_init(void)
301{
302 uint32_t mem0_base, mem0_size;
303 uint32_t io_base, io_size;
304
305 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
306 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
307 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
308 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
309
310 /*
311 * Here we assume the I/O window of second bus to be contiguous with
312 * the first. A gap is no problem but would waste address space for
313 * remapping the port space.
314 */
315 mv_pci_io_mem1_resource.start = mv_io_size;
316 mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
317 mv_pci_mem1_resource.start = mem0_base;
318 mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
319 mv_bus1_controller.pcic.mem_offset = mem0_base;
320 mv_bus1_controller.pcic.io_offset = 0;
321
322 ioport_resource.end = io_base + io_size -mv_io_base - 1;
323
324 register_pci_controller(&mv_bus1_controller.pcic);
325
326 mv_io_size = io_base + io_size - mv_io_base;
327}
328
329static __init int __init ja_pci_init(void)
330{
331 unsigned long io_v_base;
332 uint32_t enable;
333
334 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
335
336 /*
337 * We require at least one enabled I/O or PCI memory window or we
338 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
339 */
340 if (enable & (0x01 << 9) || enable & (0x01 << 10))
341 ja_pci0_init();
342
343 if (enable & (0x01 << 14) || enable & (0x01 << 15))
344 ja_pci1_init();
345
346 if (mv_io_size) {
347 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
348 if (!io_v_base)
349 panic("Could not ioremap I/O port range");
350
351 set_io_port_base(io_v_base);
352 }
353
354 return 0;
355}
356
357arch_initcall(ja_pci_init);
358
359void __init plat_mem_setup(void)
360{
361 unsigned int tmpword;
362
363 board_time_init = momenco_time_init;
364
365 _machine_restart = momenco_jaguar_restart;
366 _machine_halt = momenco_jaguar_halt;
367 pm_power_off = momenco_jaguar_power_off;
368
369 /*
370 * initrd_start = (unsigned long)jaguar_initrd_start;
371 * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size;
372 * initrd_below_start_ok = 1;
373 */
374
375 wire_stupidity_into_tlb();
376
377 /*
378 * shut down ethernet ports, just to be sure our memory doesn't get
379 * corrupted by random ethernet traffic.
380 */
381 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
382 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
383 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
384 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
385 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
386 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
387 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
388 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
389 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
390 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
391 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
392 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
393 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
394 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
395 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
396 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
397 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
398 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
399
400 /* Turn off the Bit-Error LED */
401 JAGUAR_FPGA_WRITE(0x80, CLR);
402
403 tmpword = JAGUAR_FPGA_READ(BOARDREV);
404 if (tmpword < 26)
405 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
406 'A'+tmpword);
407 else
408 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
409 tmpword);
410
411 tmpword = JAGUAR_FPGA_READ(FPGA_REV);
412 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
413 tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
414 printk("Reset reason: 0x%x\n", tmpword);
415 switch (tmpword) {
416 case 0x1:
417 printk(" - Power-up reset\n");
418 break;
419 case 0x2:
420 printk(" - Push-button reset\n");
421 break;
422 case 0x8:
423 printk(" - Watchdog reset\n");
424 break;
425 case 0x10:
426 printk(" - JTAG reset\n");
427 break;
428 default:
429 printk(" - Unknown reset cause\n");
430 }
431 reset_reason = tmpword;
432 JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
433
434 tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
435 printk("Board Status register: 0x%02x\n", tmpword);
436 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
437 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
438
439 /* 256MiB of RM9000x2 DDR */
440// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
441
442 /* 128MiB of MV-64340 DDR */
443// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
444
445 /* XXX Memory configuration should be picked up from PMON2k */
446#ifdef CONFIG_JAGUAR_DMALOW
447 printk("Jaguar ATX DMA-low mode set\n");
448 add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
449 add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
450#else
451 /* 128MiB of MV-64340 DDR RAM */
452 printk("Jaguar ATX DMA-low mode is not set\n");
453 add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
454#endif
455
456#ifdef GEMDEBUG_TRACEBUFFER
457 {
458 unsigned int tbControl;
459 tbControl =
460 0 << 26 | /* post trigger delay 0 */
461 0x2 << 16 | /* sequential trace mode */
462 // 0x0 << 16 | /* non-sequential trace mode */
463 // 0xf << 4 | /* watchpoints disabled */
464 2 << 2 | /* armed */
465 2 ; /* interrupt disabled */
466 printk ("setting tbControl = %08lx\n", tbControl);
467 write_32bit_cp0_set1_register($22, tbControl);
468 __asm__ __volatile__(".set noreorder\n\t" \
469 "nop; nop; nop; nop; nop; nop;\n\t" \
470 "nop; nop; nop; nop; nop; nop;\n\t" \
471 ".set reorder\n\t");
472
473 }
474#endif
475}
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