7 files changed, 399 insertions, 16 deletions

diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 95ba32b5b720..d7ec95522292 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_SB1)		+= c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
 obj-$(CONFIG_CPU_TX39XX)        += c-tx39.o tlb-r3k.o
 obj-$(CONFIG_CPU_TX49XX)        += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_VR41XX)        += c-r4k.o cex-gen.o tlb-r4k.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
 
 obj-$(CONFIG_IP22_CPU_SCACHE)   += sc-ip22.o
 obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
new file mode 100644
index 000000000000..44d01a0a8490
--- /dev/null
+++ b/arch/mips/mm/c-octeon.c
@@ -0,0 +1,307 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2007 Cavium Networks
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/bitops.h>
+#include <linux/cpu.h>
+#include <linux/io.h>
+
+#include <asm/bcache.h>
+#include <asm/bootinfo.h>
+#include <asm/cacheops.h>
+#include <asm/cpu-features.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/r4kcache.h>
+#include <asm/system.h>
+#include <asm/mmu_context.h>
+#include <asm/war.h>
+
+#include <asm/octeon/octeon.h>
+
+unsigned long long cache_err_dcache[NR_CPUS];
+
+/**
+ * Octeon automatically flushes the dcache on tlb changes, so
+ * from Linux's viewpoint it acts much like a physically
+ * tagged cache. No flushing is needed
+ *
+ */
+static void octeon_flush_data_cache_page(unsigned long addr)
+{
+    /* Nothing to do */
+}
+
+static inline void octeon_local_flush_icache(void)
+{
+        asm volatile ("synci 0($0)");
+}
+
+/*
+ * Flush local I-cache for the specified range.
+ */
+static void local_octeon_flush_icache_range(unsigned long start,
+                                            unsigned long end)
+{
+        octeon_local_flush_icache();
+}
+
+/**
+ * Flush caches as necessary for all cores affected by a
+ * vma. If no vma is supplied, all cores are flushed.
+ *
+ * @vma:    VMA to flush or NULL to flush all icaches.
+ */
+static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
+{
+        extern void octeon_send_ipi_single(int cpu, unsigned int action);
+#ifdef CONFIG_SMP
+        int cpu;
+        cpumask_t mask;
+#endif
+
+        mb();
+        octeon_local_flush_icache();
+#ifdef CONFIG_SMP
+        preempt_disable();
+        cpu = smp_processor_id();
+
+        /*
+         * If we have a vma structure, we only need to worry about
+         * cores it has been used on
+         */
+        if (vma)
+                mask = vma->vm_mm->cpu_vm_mask;
+        else
+                mask = cpu_online_map;
+        cpu_clear(cpu, mask);
+        for_each_cpu_mask(cpu, mask)
+                octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
+
+        preempt_enable();
+#endif
+}
+
+
+/**
+ * Called to flush the icache on all cores
+ */
+static void octeon_flush_icache_all(void)
+{
+        octeon_flush_icache_all_cores(NULL);
+}
+
+
+/**
+ * Called to flush all memory associated with a memory
+ * context.
+ *
+ * @mm:     Memory context to flush
+ */
+static void octeon_flush_cache_mm(struct mm_struct *mm)
+{
+        /*
+         * According to the R4K version of this file, CPUs without
+         * dcache aliases don't need to do anything here
+         */
+}
+
+
+/**
+ * Flush a range of kernel addresses out of the icache
+ *
+ */
+static void octeon_flush_icache_range(unsigned long start, unsigned long end)
+{
+        octeon_flush_icache_all_cores(NULL);
+}
+
+
+/**
+ * Flush the icache for a trampoline. These are used for interrupt
+ * and exception hooking.
+ *
+ * @addr:   Address to flush
+ */
+static void octeon_flush_cache_sigtramp(unsigned long addr)
+{
+        struct vm_area_struct *vma;
+
+        vma = find_vma(current->mm, addr);
+        octeon_flush_icache_all_cores(vma);
+}
+
+
+/**
+ * Flush a range out of a vma
+ *
+ * @vma:    VMA to flush
+ * @start:
+ * @end:
+ */
+static void octeon_flush_cache_range(struct vm_area_struct *vma,
+                                     unsigned long start, unsigned long end)
+{
+        if (vma->vm_flags & VM_EXEC)
+                octeon_flush_icache_all_cores(vma);
+}
+
+
+/**
+ * Flush a specific page of a vma
+ *
+ * @vma:    VMA to flush page for
+ * @page:   Page to flush
+ * @pfn:
+ */
+static void octeon_flush_cache_page(struct vm_area_struct *vma,
+                                    unsigned long page, unsigned long pfn)
+{
+        if (vma->vm_flags & VM_EXEC)
+                octeon_flush_icache_all_cores(vma);
+}
+
+
+/**
+ * Probe Octeon's caches
+ *
+ */
+static void __devinit probe_octeon(void)
+{
+        unsigned long icache_size;
+        unsigned long dcache_size;
+        unsigned int config1;
+        struct cpuinfo_mips *c = &current_cpu_data;
+
+        switch (c->cputype) {
+        case CPU_CAVIUM_OCTEON:
+                config1 = read_c0_config1();
+                c->icache.linesz = 2 << ((config1 >> 19) & 7);
+                c->icache.sets = 64 << ((config1 >> 22) & 7);
+                c->icache.ways = 1 + ((config1 >> 16) & 7);
+                c->icache.flags |= MIPS_CACHE_VTAG;
+                icache_size =
+                        c->icache.sets * c->icache.ways * c->icache.linesz;
+                c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
+                c->dcache.linesz = 128;
+                if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        c->dcache.sets = 1; /* CN3XXX has one Dcache set */
+                else
+                        c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
+                c->dcache.ways = 64;
+                dcache_size =
+                        c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+                c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
+                c->options |= MIPS_CPU_PREFETCH;
+                break;
+
+        default:
+                panic("Unsupported Cavium Networks CPU type\n");
+                break;
+        }
+
+        /* compute a couple of other cache variables */
+        c->icache.waysize = icache_size / c->icache.ways;
+        c->dcache.waysize = dcache_size / c->dcache.ways;
+
+        c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
+        c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
+
+        if (smp_processor_id() == 0) {
+                pr_notice("Primary instruction cache %ldkB, %s, %d way, "
+                          "%d sets, linesize %d bytes.\n",
+                          icache_size >> 10,
+                          cpu_has_vtag_icache ?
+                                "virtually tagged" : "physically tagged",
+                          c->icache.ways, c->icache.sets, c->icache.linesz);
+
+                pr_notice("Primary data cache %ldkB, %d-way, %d sets, "
+                          "linesize %d bytes.\n",
+                          dcache_size >> 10, c->dcache.ways,
+                          c->dcache.sets, c->dcache.linesz);
+        }
+}
+
+
+/**
+ * Setup the Octeon cache flush routines
+ *
+ */
+void __devinit octeon_cache_init(void)
+{
+        extern unsigned long ebase;
+        extern char except_vec2_octeon;
+
+        memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80);
+        octeon_flush_cache_sigtramp(ebase + 0x100);
+
+        probe_octeon();
+
+        shm_align_mask = PAGE_SIZE - 1;
+
+        flush_cache_all                 = octeon_flush_icache_all;
+        __flush_cache_all               = octeon_flush_icache_all;
+        flush_cache_mm                  = octeon_flush_cache_mm;
+        flush_cache_page                = octeon_flush_cache_page;
+        flush_cache_range               = octeon_flush_cache_range;
+        flush_cache_sigtramp            = octeon_flush_cache_sigtramp;
+        flush_icache_all                = octeon_flush_icache_all;
+        flush_data_cache_page           = octeon_flush_data_cache_page;
+        flush_icache_range              = octeon_flush_icache_range;
+        local_flush_icache_range        = local_octeon_flush_icache_range;
+
+        build_clear_page();
+        build_copy_page();
+}
+
+/**
+ * Handle a cache error exception
+ */
+
+static void  cache_parity_error_octeon(int non_recoverable)
+{
+        unsigned long coreid = cvmx_get_core_num();
+        uint64_t icache_err = read_octeon_c0_icacheerr();
+
+        pr_err("Cache error exception:\n");
+        pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
+        if (icache_err & 1) {
+                pr_err("CacheErr (Icache) == %llx\n",
+                       (unsigned long long)icache_err);
+                write_octeon_c0_icacheerr(0);
+        }
+        if (cache_err_dcache[coreid] & 1) {
+                pr_err("CacheErr (Dcache) == %llx\n",
+                       (unsigned long long)cache_err_dcache[coreid]);
+                cache_err_dcache[coreid] = 0;
+        }
+
+        if (non_recoverable)
+                panic("Can't handle cache error: nested exception");
+}
+
+/**
+ * Called when the the exception is not recoverable
+ */
+
+asmlinkage void cache_parity_error_octeon_recoverable(void)
+{
+        cache_parity_error_octeon(0);
+}
+
+/**
+ * Called when the the exception is recoverable
+ */
+
+asmlinkage void cache_parity_error_octeon_non_recoverable(void)
+{
+        cache_parity_error_octeon(1);
+}
+
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 1eb7c71e3d6a..98ad0a82c29e 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -182,6 +182,12 @@ void __devinit cpu_cache_init(void)
                 tx39_cache_init();
         }
 
+        if (cpu_has_octeon_cache) {
+                extern void __weak octeon_cache_init(void);
+
+                octeon_cache_init();
+        }
+
         setup_protection_map();
 }
 
diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S
new file mode 100644
index 000000000000..3db8553fcd34
--- /dev/null
+++ b/arch/mips/mm/cex-oct.S
@@ -0,0 +1,70 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Cavium Networks
+ * Cache error handler
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+
+/*
+ * Handle cache error. Indicate to the second level handler whether
+ * the exception is recoverable.
+ */
+        LEAF(except_vec2_octeon)
+
+        .set    push
+        .set    mips64r2
+        .set    noreorder
+        .set    noat
+
+
+        /* due to an errata we need to read the COP0 CacheErr (Dcache)
+         * before any cache/DRAM access  */
+
+        rdhwr   k0, $0        /* get core_id */
+        PTR_LA  k1, cache_err_dcache
+        sll     k0, k0, 3
+        PTR_ADDU k1, k0, k1    /* k1 = &cache_err_dcache[core_id] */
+
+        dmfc0   k0, CP0_CACHEERR, 1
+        sd      k0, (k1)
+        dmtc0   $0, CP0_CACHEERR, 1
+
+        /* check whether this is a nested exception */
+        mfc0    k1, CP0_STATUS
+        andi    k1, k1, ST0_EXL
+        beqz    k1, 1f
+         nop
+        j       cache_parity_error_octeon_non_recoverable
+         nop
+
+        /* exception is recoverable */
+1:      j       handle_cache_err
+         nop
+
+        .set    pop
+        END(except_vec2_octeon)
+
+ /* We need to jump to handle_cache_err so that the previous handler
+  * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX
+  * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached).  */
+        LEAF(handle_cache_err)
+        .set    push
+        .set    noreorder
+        .set    noat
+
+        SAVE_ALL
+        KMODE
+        jal     cache_parity_error_octeon_recoverable
+        nop
+        j       ret_from_exception
+        nop
+
+        .set pop
+        END(handle_cache_err)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index e6708b3ad343..546e6977d4ff 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -111,7 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent);
 void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
         dma_addr_t dma_handle)
 {
-        plat_unmap_dma_mem(dma_handle);
+        plat_unmap_dma_mem(dev, dma_handle);
         free_pages((unsigned long) vaddr, get_order(size));
 }
 
@@ -122,7 +122,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 {
         unsigned long addr = (unsigned long) vaddr;
 
-        plat_unmap_dma_mem(dma_handle);
+        plat_unmap_dma_mem(dev, dma_handle);
 
         if (!plat_device_is_coherent(dev))
                 addr = CAC_ADDR(addr);
@@ -173,7 +173,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                 __dma_sync(dma_addr_to_virt(dma_addr), size,
                            direction);
 
-        plat_unmap_dma_mem(dma_addr);
+        plat_unmap_dma_mem(dev, dma_addr);
 }
 
 EXPORT_SYMBOL(dma_unmap_single);
@@ -229,7 +229,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
                 dma_cache_wback_inv(addr, size);
         }
 
-        plat_unmap_dma_mem(dma_address);
+        plat_unmap_dma_mem(dev, dma_address);
 }
 
 EXPORT_SYMBOL(dma_unmap_page);
@@ -249,7 +249,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
                         if (addr)
                                 __dma_sync(addr, sg->length, direction);
                 }
-                plat_unmap_dma_mem(sg->dma_address);
+                plat_unmap_dma_mem(dev, sg->dma_address);
         }
 }
 
@@ -275,6 +275,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
 {
         BUG_ON(direction == DMA_NONE);
 
+        plat_extra_sync_for_device(dev);
         if (!plat_device_is_coherent(dev)) {
                 unsigned long addr;
 
@@ -305,6 +306,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
 {
         BUG_ON(direction == DMA_NONE);
 
+        plat_extra_sync_for_device(dev);
         if (!plat_device_is_coherent(dev)) {
                 unsigned long addr;
 
@@ -351,22 +353,14 @@ EXPORT_SYMBOL(dma_sync_sg_for_device);
 
 int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
-        return 0;
+        return plat_dma_mapping_error(dev, dma_addr);
 }
 
 EXPORT_SYMBOL(dma_mapping_error);
 
 int dma_supported(struct device *dev, u64 mask)
 {
-        /*
-         * we fall back to GFP_DMA when the mask isn't all 1s,
-         * so we can't guarantee allocations that must be
-         * within a tighter range than GFP_DMA..
-         */
-        if (mask < DMA_BIT_MASK(24))
-                return 0;
-
-        return 1;
+        return plat_dma_supported(dev, mask);
 }
 
 EXPORT_SYMBOL(dma_supported);
@@ -383,6 +377,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 {
         BUG_ON(direction == DMA_NONE);
 
+        plat_extra_sync_for_device(dev);
         if (!plat_device_is_coherent(dev))
                 __dma_sync((unsigned long)vaddr, size, direction);
 }
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 5ce2fa745626..9619f66e531e 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -478,7 +478,10 @@ void __cpuinit tlb_init(void)
         probe_tlb(config);
         write_c0_pagemask(PM_DEFAULT_MASK);
         write_c0_wired(0);
-        write_c0_framemask(0);
+        if (current_cpu_type() == CPU_R10000 ||
+            current_cpu_type() == CPU_R12000 ||
+            current_cpu_type() == CPU_R14000)
+                write_c0_framemask(0);
         temp_tlb_entry = current_cpu_data.tlbsize - 1;
 
         /* From this point on the ARC firmware is dead.  */
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 979cf9197282..42942038d0fd 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -317,6 +317,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_BCM3302:
         case CPU_BCM4710:
         case CPU_LOONGSON2:
+        case CPU_CAVIUM_OCTEON:
                 if (m4kc_tlbp_war())
                         uasm_i_nop(p);
                 tlbw(p);