1 files changed, 5 insertions, 0 deletions

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 86f004dc8355..4510e61883eb 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
                 tlbw(p);
                 break;
 
+        case CPU_JZRISC:
+                tlbw(p);
+                uasm_i_nop(p);
+                break;
+
         default:
                 panic("No TLB refill handler yet (CPU type: %d)",
                       current_cpu_data.cputype);