2 files changed, 61 insertions, 47 deletions

diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index 4f770ac885ce..9185fbf37c0d 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -4,6 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2007  Maciej W. Rozycki
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -12,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/proc_fs.h>
 
+#include <asm/bugs.h>
 #include <asm/cacheops.h>
 #include <asm/inst.h>
 #include <asm/io.h>
@@ -255,64 +257,58 @@ static inline void build_store_reg(int reg)
         __build_store_reg(reg);
 }
 
-static inline void build_addiu_a2_a0(unsigned long offset)
+static inline void build_addiu_rt_rs(unsigned int rt, unsigned int rs,
+                                     unsigned long offset)
 {
         union mips_instruction mi;
 
         BUG_ON(offset > 0x7fff);
 
-        mi.i_format.opcode     = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
-        mi.i_format.rs         = 4;             /* $a0 */
-        mi.i_format.rt         = 6;             /* $a2 */
-        mi.i_format.simmediate = offset;
+        if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
+                mi.i_format.opcode     = addiu_op;
+                mi.i_format.rs         = 0;     /* $zero */
+                mi.i_format.rt         = 25;    /* $t9 */
+                mi.i_format.simmediate = offset;
+                emit_instruction(mi);
 
+                mi.r_format.opcode     = spec_op;
+                mi.r_format.rs         = rs;
+                mi.r_format.rt         = 25;    /* $t9 */
+                mi.r_format.rd         = rt;
+                mi.r_format.re         = 0;
+                mi.r_format.func       = daddu_op;
+        } else {
+                mi.i_format.opcode     = cpu_has_64bit_gp_regs ?
+                                         daddiu_op : addiu_op;
+                mi.i_format.rs         = rs;
+                mi.i_format.rt         = rt;
+                mi.i_format.simmediate = offset;
+        }
         emit_instruction(mi);
 }
 
-static inline void build_addiu_a2(unsigned long offset)
+static inline void build_addiu_a2_a0(unsigned long offset)
 {
-        union mips_instruction mi;
-
-        BUG_ON(offset > 0x7fff);
-
-        mi.i_format.opcode     = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
-        mi.i_format.rs         = 6;             /* $a2 */
-        mi.i_format.rt         = 6;             /* $a2 */
-        mi.i_format.simmediate = offset;
+        build_addiu_rt_rs(6, 4, offset);        /* $a2, $a0, offset */
+}
 
-        emit_instruction(mi);
+static inline void build_addiu_a2(unsigned long offset)
+{
+        build_addiu_rt_rs(6, 6, offset);        /* $a2, $a2, offset */
 }
 
 static inline void build_addiu_a1(unsigned long offset)
 {
-        union mips_instruction mi;
-
-        BUG_ON(offset > 0x7fff);
-
-        mi.i_format.opcode     = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
-        mi.i_format.rs         = 5;             /* $a1 */
-        mi.i_format.rt         = 5;             /* $a1 */
-        mi.i_format.simmediate = offset;
+        build_addiu_rt_rs(5, 5, offset);        /* $a1, $a1, offset */
 
         load_offset -= offset;
-
-        emit_instruction(mi);
 }
 
 static inline void build_addiu_a0(unsigned long offset)
 {
-        union mips_instruction mi;
-
-        BUG_ON(offset > 0x7fff);
-
-        mi.i_format.opcode     = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
-        mi.i_format.rs         = 4;             /* $a0 */
-        mi.i_format.rt         = 4;             /* $a0 */
-        mi.i_format.simmediate = offset;
+        build_addiu_rt_rs(4, 4, offset);        /* $a0, $a0, offset */
 
         store_offset -= offset;
-
-        emit_instruction(mi);
 }
 
 static inline void build_bne(unsigned int *dest)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 511107f92d9c..f8925ba0b39e 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -6,7 +6,7 @@
  * Synthesize TLB refill handlers at runtime.
  *
  * Copyright (C) 2004,2005,2006 by Thiemo Seufer
- * Copyright (C) 2005  Maciej W. Rozycki
+ * Copyright (C) 2005, 2007  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  *
  * ... and the days got worse and worse and now you see
@@ -27,6 +27,7 @@
 #include <linux/string.h>
 #include <linux/init.h>
 
+#include <asm/bugs.h>
 #include <asm/pgtable.h>
 #include <asm/cacheflush.h>
 #include <asm/mmu_context.h>
@@ -293,7 +294,7 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...)
                         break;
                 }
 
-        if (!ip)
+        if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
                 panic("Unsupported TLB synthesizer instruction %d", opc);
 
         op = ip->match;
@@ -525,23 +526,33 @@ L_LA(_r3000_write_probe_fail)
 #define i_ssnop(buf) i_sll(buf, 0, 0, 1)
 #define i_ehb(buf) i_sll(buf, 0, 0, 3)
 
-#ifdef CONFIG_64BIT
 static __init int __maybe_unused in_compat_space_p(long addr)
 {
         /* Is this address in 32bit compat space? */
+#ifdef CONFIG_64BIT
         return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
+#else
+        return 1;
+#endif
 }
 
 static __init int __maybe_unused rel_highest(long val)
 {
+#ifdef CONFIG_64BIT
         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
+#else
+        return 0;
+#endif
 }
 
 static __init int __maybe_unused rel_higher(long val)
 {
+#ifdef CONFIG_64BIT
         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
-}
+#else
+        return 0;
 #endif
+}
 
 static __init int rel_hi(long val)
 {
@@ -555,7 +566,6 @@ static __init int rel_lo(long val)
 
 static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
 {
-#ifdef CONFIG_64BIT
         if (!in_compat_space_p(addr)) {
                 i_lui(buf, rs, rel_highest(addr));
                 if (rel_higher(addr))
@@ -567,16 +577,18 @@ static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
                 } else
                         i_dsll32(buf, rs, rs, 0);
         } else
-#endif
                 i_lui(buf, rs, rel_hi(addr));
 }
 
-static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs,
-                                             long addr)
+static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs, long addr)
 {
         i_LA_mostly(buf, rs, addr);
-        if (rel_lo(addr))
-                i_ADDIU(buf, rs, rs, rel_lo(addr));
+        if (rel_lo(addr)) {
+                if (!in_compat_space_p(addr))
+                        i_daddiu(buf, rs, rs, rel_lo(addr));
+                else
+                        i_addiu(buf, rs, rs, rel_lo(addr));
+        }
 }
 
 /*
@@ -1085,7 +1097,10 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
         } else {
                 i_LA_mostly(p, ptr, modd);
                 il_b(p, r, label_vmalloc_done);
-                i_daddiu(p, ptr, ptr, rel_lo(modd));
+                if (in_compat_space_p(modd))
+                        i_addiu(p, ptr, ptr, rel_lo(modd));
+                else
+                        i_daddiu(p, ptr, ptr, rel_lo(modd));
         }
 
         l_vmalloc(l, *p);
@@ -1106,7 +1121,10 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
         } else {
                 i_LA_mostly(p, ptr, swpd);
                 il_b(p, r, label_vmalloc_done);
-                i_daddiu(p, ptr, ptr, rel_lo(swpd));
+                if (in_compat_space_p(swpd))
+                        i_addiu(p, ptr, ptr, rel_lo(swpd));
+                else
+                        i_daddiu(p, ptr, ptr, rel_lo(swpd));
         }
 }