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-rw-r--r--arch/mips/mm/tlbex.c9
1 files changed, 3 insertions, 6 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 325bc730ab5e..21bcf084882f 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1391,18 +1391,15 @@ static void __init build_r4000_tlb_refill_handler(void)
1391extern void tlb_do_page_fault_0(void); 1391extern void tlb_do_page_fault_0(void);
1392extern void tlb_do_page_fault_1(void); 1392extern void tlb_do_page_fault_1(void);
1393 1393
1394#define __tlb_handler_align \
1395 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1396
1397/* 1394/*
1398 * 128 instructions for the fastpath handler is generous and should 1395 * 128 instructions for the fastpath handler is generous and should
1399 * never be exceeded. 1396 * never be exceeded.
1400 */ 1397 */
1401#define FASTPATH_SIZE 128 1398#define FASTPATH_SIZE 128
1402 1399
1403u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; 1400u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
1404u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; 1401u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
1405u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; 1402u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
1406 1403
1407static void __init 1404static void __init
1408iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) 1405iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)